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https://github.com/brain-hackers/u-boot-brain
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![Wolfgang Denk](/assets/img/avatar_default.png)
This commit gets rid of a huge amount of silly white-space issues. Especially, all sequences of SPACEs followed by TAB characters get removed (unless they appear in print statements). Also remove all embedded "vim:" and "vi:" statements which hide indentation problems. Signed-off-by: Wolfgang Denk <wd@denx.de>
67 lines
2.0 KiB
ArmAsm
67 lines
2.0 KiB
ArmAsm
/*
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* Initialization stuff - taken from hermit
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* (C) Copyright 2005 Rowel Atienza <rowel@diwalabs.com>
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* Armadillo board HT1070
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <config.h>
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#include <version.h>
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/* some parameters for the board */
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/* setting up the memory */
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#define SRAM_START 0x60000000
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#define SRAM_SIZE 0x0000c000
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.globl lowlevel_init
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lowlevel_init:
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mov r0, #0x70 /* 32-bit code + data, MMU mandatory */
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mcr p15, 0, r0, c1, c0, 0 /* MMU init */
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mov r0, #0
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mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */
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mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
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mov r0, #0x80000000 /* I/O base */
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mov r1, #0x6 /* CLKCTL_73 in SYSCON3 */
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add r2, r0, #0x2200 /* address of SYSCON3 in r2 */
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str r1, [r2] /* set clock speed to 73.728 MHz */
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mov r1, #0x81 /* 64KHz DRAM refresh period */
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str r1, [r0, #0x200] /* set DRFPR */
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mov r1, #0x500 /* permanent enable, 16bits wide */
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add r1, r1, #0x42 /* 128Mbit, CAS lat = 2 SDRAM */
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add r2, r0, #0x2300 /* load address in r2 */
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str r1, [r2]
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mov r1, #0x100 /* SDRAM refresh rate */
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add r2, r0, #0x2340 /* load address in r2 */
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str r1, [r2]
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mov sp, #SRAM_START /* init stack pointer */
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add sp, sp, #SRAM_SIZE
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/* everything is fine now */
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mov pc, lr
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