mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-09-08 13:53:21 +09:00
5e4a6db8f4
On LS1012ARDB board, three dual 1:4 mux/demux devices drive the SDHC2 signals to eMMC, SDIO wifi, SPI and Ardiuno shield. Only when we select eMMC and SDIO wifi, the SDHC2 could be used. Otherwise, the command inhibit bits of eSDHC2_PRSSTAT register will never release. This would cause below continious error messages in linux since it uses polling mode to detect card. "mmc1: Controller never released inhibit bit(s)." "mmc1: Controller never released inhibit bit(s)." "mmc1: Controller never released inhibit bit(s)." This patch is to define esdhc_status_fixup function for RDB to disable SDHC2 status if no SDIO wifi or eMMC is selected. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
162 lines
3.3 KiB
C
162 lines
3.3 KiB
C
/*
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* Copyright 2016 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <i2c.h>
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/fsl_serdes.h>
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#include <asm/arch/soc.h>
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#include <hwconfig.h>
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#include <ahci.h>
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#include <mmc.h>
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#include <scsi.h>
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#include <fsl_esdhc.h>
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#include <environment.h>
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#include <fsl_mmdc.h>
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#include <netdev.h>
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DECLARE_GLOBAL_DATA_PTR;
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int checkboard(void)
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{
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u8 in1;
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puts("Board: LS1012ARDB ");
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/* Initialize i2c early for Serial flash bank information */
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i2c_set_bus_num(0);
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if (i2c_read(I2C_MUX_IO1_ADDR, 1, 1, &in1, 1) < 0) {
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printf("Error reading i2c boot information!\n");
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return 0; /* Don't want to hang() on this error */
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}
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puts("Version");
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if ((in1 & (~__SW_REV_MASK)) == __SW_REV_A)
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puts(": RevA");
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else if ((in1 & (~__SW_REV_MASK)) == __SW_REV_B)
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puts(": RevB");
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else
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puts(": unknown");
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printf(", boot from QSPI");
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if ((in1 & (~__SW_BOOT_MASK)) == __SW_BOOT_EMU)
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puts(": emu\n");
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else if ((in1 & (~__SW_BOOT_MASK)) == __SW_BOOT_BANK1)
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puts(": bank1\n");
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else if ((in1 & (~__SW_BOOT_MASK)) == __SW_BOOT_BANK2)
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puts(": bank2\n");
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else
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puts("unknown\n");
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return 0;
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}
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int dram_init(void)
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{
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static const struct fsl_mmdc_info mparam = {
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0x05180000, /* mdctl */
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0x00030035, /* mdpdc */
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0x12554000, /* mdotc */
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0xbabf7954, /* mdcfg0 */
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0xdb328f64, /* mdcfg1 */
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0x01ff00db, /* mdcfg2 */
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0x00001680, /* mdmisc */
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0x0f3c8000, /* mdref */
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0x00002000, /* mdrwd */
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0x00bf1023, /* mdor */
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0x0000003f, /* mdasp */
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0x0000022a, /* mpodtctrl */
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0xa1390003, /* mpzqhwctrl */
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};
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mmdc_init(&mparam);
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gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
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return 0;
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}
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int board_eth_init(bd_t *bis)
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{
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return pci_eth_init(bis);
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}
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int board_early_init_f(void)
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{
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fsl_lsch2_early_init_f();
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return 0;
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}
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int board_init(void)
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{
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struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
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/*
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* Set CCI-400 control override register to enable barrier
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* transaction
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*/
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out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
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#ifdef CONFIG_SYS_FSL_ERRATUM_A010315
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erratum_a010315();
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#endif
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#ifdef CONFIG_ENV_IS_NOWHERE
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gd->env_addr = (ulong)&default_environment[0];
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#endif
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return 0;
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}
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int esdhc_status_fixup(void *blob, const char *compat)
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{
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char esdhc0_path[] = "/soc/esdhc@1560000";
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char esdhc1_path[] = "/soc/esdhc@1580000";
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u8 io = 0;
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u8 mux_sdhc2;
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do_fixup_by_path(blob, esdhc0_path, "status", "okay",
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sizeof("okay"), 1);
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i2c_set_bus_num(0);
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/*
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* The I2C IO-expander for mux select is used to control the muxing
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* of various onboard interfaces.
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*
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* IO1[3:2] indicates SDHC2 interface demultiplexer select lines.
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* 00 - SDIO wifi
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* 01 - GPIO (to Arduino)
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* 10 - eMMC Memory
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* 11 - SPI
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*/
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if (i2c_read(I2C_MUX_IO1_ADDR, 0, 1, &io, 1) < 0) {
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printf("Error reading i2c boot information!\n");
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return 0; /* Don't want to hang() on this error */
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}
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mux_sdhc2 = (io & 0x0c) >> 2;
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/* Enable SDHC2 only when use SDIO wifi and eMMC */
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if (mux_sdhc2 == 2 || mux_sdhc2 == 0)
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do_fixup_by_path(blob, esdhc1_path, "status", "okay",
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sizeof("okay"), 1);
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else
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do_fixup_by_path(blob, esdhc1_path, "status", "disabled",
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sizeof("disabled"), 1);
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return 0;
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}
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int ft_board_setup(void *blob, bd_t *bd)
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{
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arch_fixup_fdt(blob);
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ft_cpu_setup(blob, bd);
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return 0;
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}
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