mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-21 02:28:00 +09:00
65dd74a674
Implement SDRAM init using the Memory Reference Code (mrc.bin) provided in the board directory and the SDRAM SPD information in the device tree. This also needs the Intel Management Engine (me.bin) to work. Binary blobs everywhere: so far we have MRC, ME and microcode. SDRAM init works by setting up various parameters and calling the MRC. This in turn does some sort of magic to work out how much memory there is and the timing parameters to use. It also sets up the DRAM controllers. When the MRC returns, we use the information it provides to map out the available memory in U-Boot. U-Boot normally moves itself to the top of RAM. On x86 the RAM is not generally contiguous, and anyway some RAM may be above 4GB which doesn't work in 32-bit mode. So we relocate to the top of the largest block of RAM we can find below 4GB. Memory above 4GB is accessible with special functions (see physmem). It would be possible to build U-Boot in 64-bit mode but this wouldn't necessarily provide any more memory, since the largest block is often below 4GB. Anyway U-Boot doesn't need huge amounts of memory - even a very large ramdisk seldom exceeds 100-200MB. U-Boot has support for booting 64-bit kernels directly so this does not pose a limitation in that area. Also there are probably parts of U-Boot that will not work correctly in 64-bit mode. The MRC is one. There is some work remaining in this area. Since memory init is very slow (over 500ms) it is possible to save the parameters in SPI flash to speed it up next time. Suspend/resume support is not fully implemented, or at least it is not efficient. With this patch, link boots to a prompt. Signed-off-by: Simon Glass <sjg@chromium.org>
51 lines
1.0 KiB
C
51 lines
1.0 KiB
C
/*
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* Copyright (c) 2014 Google, Inc
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _post_h
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#define _post_h
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/* port to use for post codes */
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#define POST_PORT 0x80
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/* post codes which represent various stages of init */
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#define POST_START 0x1e
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#define POST_CAR_START 0x1f
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#define POST_CAR_SIPI 0x20
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#define POST_CAR_MTRR 0x21
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#define POST_CAR_UNCACHEABLE 0x22
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#define POST_CAR_BASE_ADDRESS 0x23
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#define POST_CAR_MASK 0x24
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#define POST_CAR_FILL 0x25
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#define POST_CAR_ROM_CACHE 0x26
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#define POST_CAR_MRC_CACHE 0x27
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#define POST_CAR_CPU_CACHE 0x28
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#define POST_START_STACK 0x29
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#define POST_START_DONE 0x2a
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#define POST_CPU_INIT 0x2b
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#define POST_EARLY_INIT 0x2c
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#define POST_CPU_INFO 0x2d
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#define POST_PRE_MRC 0x2e
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#define POST_MRC 0x2f
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#define POST_DRAM 0x2f
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#define POST_RAM_FAILURE 0xea
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/* Output a post code using al - value must be 0 to 0xff */
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#ifdef __ASSEMBLY__
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#define post_code(value) \
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movb $value, %al; \
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outb %al, $POST_PORT
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#else
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#include <asm/io.h>
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static inline void post_code(int code)
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{
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outb(code, POST_PORT);
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}
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#endif
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#endif
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