mirror of
https://github.com/brain-hackers/u-boot-brain
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4e5439ac25
The warm-reset of rk3188 socs keeps the remap setting as it was, so if it was enabled, the cpu would start from address 0x0 of the sram instead of address 0x0 of the bootrom, thus making the reset hang. Therefore make sure the remap is disabled before attempting a warm reset. Cold reset is not affected by this at all. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Simon Glass <sjg@chromium.org>
63 lines
1.3 KiB
C
63 lines
1.3 KiB
C
/*
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* (C) Copyright 2015 Google, Inc
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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#include <common.h>
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#include <dm.h>
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#include <errno.h>
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#include <syscon.h>
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#include <sysreset.h>
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/cru_rk3188.h>
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#include <asm/arch/grf_rk3188.h>
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#include <asm/arch/hardware.h>
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#include <linux/err.h>
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int rk3188_sysreset_request(struct udevice *dev, enum sysreset_t type)
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{
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struct rk3188_cru *cru = rockchip_get_cru();
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struct rk3188_grf *grf;
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if (IS_ERR(cru))
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return PTR_ERR(cru);
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switch (type) {
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case SYSRESET_WARM:
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grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
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if (IS_ERR(grf))
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return -EPROTONOSUPPORT;
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/*
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* warm-reset keeps the remap value,
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* so make sure it's disabled.
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*/
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rk_clrsetreg(&grf->soc_con0,
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NOC_REMAP_MASK << NOC_REMAP_SHIFT,
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0 << NOC_REMAP_SHIFT);
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rk_clrreg(&cru->cru_mode_con, 0xffff);
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writel(0xeca8, &cru->cru_glb_srst_snd_value);
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break;
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case SYSRESET_COLD:
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rk_clrreg(&cru->cru_mode_con, 0xffff);
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writel(0xfdb9, &cru->cru_glb_srst_fst_value);
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break;
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default:
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return -EPROTONOSUPPORT;
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}
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return -EINPROGRESS;
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}
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static struct sysreset_ops rk3188_sysreset = {
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.request = rk3188_sysreset_request,
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};
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U_BOOT_DRIVER(sysreset_rk3188) = {
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.name = "rk3188_sysreset",
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.id = UCLASS_SYSRESET,
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.ops = &rk3188_sysreset,
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};
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