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https://github.com/brain-hackers/u-boot-brain
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![Tom Rini](/assets/img/avatar_default.png)
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
380 lines
10 KiB
C
380 lines
10 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* (C) Copyright 2015 Google, Inc
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*/
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#include <common.h>
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#include <clk-uclass.h>
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#include <dm.h>
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#include <errno.h>
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#include <syscon.h>
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/cru_rk3036.h>
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#include <asm/arch/hardware.h>
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#include <dm/lists.h>
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#include <dt-bindings/clock/rk3036-cru.h>
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#include <linux/log2.h>
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enum {
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VCO_MAX_HZ = 2400U * 1000000,
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VCO_MIN_HZ = 600 * 1000000,
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OUTPUT_MAX_HZ = 2400U * 1000000,
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OUTPUT_MIN_HZ = 24 * 1000000,
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};
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#define RATE_TO_DIV(input_rate, output_rate) \
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((input_rate) / (output_rate) - 1);
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#define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1))
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#define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\
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.refdiv = _refdiv,\
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.fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ),\
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.postdiv1 = _postdiv1, .postdiv2 = _postdiv2};\
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_Static_assert(((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ) *\
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OSC_HZ / (_refdiv * _postdiv1 * _postdiv2) == hz,\
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#hz "Hz cannot be hit with PLL "\
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"divisors on line " __stringify(__LINE__));
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/* use integer mode*/
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static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 3, 1);
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static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1);
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static int rkclk_set_pll(struct rk3036_cru *cru, enum rk_clk_id clk_id,
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const struct pll_div *div)
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{
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int pll_id = rk_pll_id(clk_id);
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struct rk3036_pll *pll = &cru->pll[pll_id];
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/* All PLLs have same VCO and output frequency range restrictions. */
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uint vco_hz = OSC_HZ / 1000 * div->fbdiv / div->refdiv * 1000;
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uint output_hz = vco_hz / div->postdiv1 / div->postdiv2;
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debug("PLL at %p: fbdiv=%d, refdiv=%d, postdiv1=%d, postdiv2=%d,\
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vco=%u Hz, output=%u Hz\n",
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pll, div->fbdiv, div->refdiv, div->postdiv1,
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div->postdiv2, vco_hz, output_hz);
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assert(vco_hz >= VCO_MIN_HZ && vco_hz <= VCO_MAX_HZ &&
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output_hz >= OUTPUT_MIN_HZ && output_hz <= OUTPUT_MAX_HZ);
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/* use integer mode */
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rk_setreg(&pll->con1, 1 << PLL_DSMPD_SHIFT);
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rk_clrsetreg(&pll->con0,
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PLL_POSTDIV1_MASK | PLL_FBDIV_MASK,
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(div->postdiv1 << PLL_POSTDIV1_SHIFT) | div->fbdiv);
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rk_clrsetreg(&pll->con1, PLL_POSTDIV2_MASK | PLL_REFDIV_MASK,
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(div->postdiv2 << PLL_POSTDIV2_SHIFT |
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div->refdiv << PLL_REFDIV_SHIFT));
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/* waiting for pll lock */
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while (readl(&pll->con1) & (1 << PLL_LOCK_STATUS_SHIFT))
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udelay(1);
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return 0;
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}
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static void rkclk_init(struct rk3036_cru *cru)
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{
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u32 aclk_div;
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u32 hclk_div;
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u32 pclk_div;
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/* pll enter slow-mode */
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rk_clrsetreg(&cru->cru_mode_con,
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GPLL_MODE_MASK | APLL_MODE_MASK,
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GPLL_MODE_SLOW << GPLL_MODE_SHIFT |
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APLL_MODE_SLOW << APLL_MODE_SHIFT);
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/* init pll */
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rkclk_set_pll(cru, CLK_ARM, &apll_init_cfg);
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rkclk_set_pll(cru, CLK_GENERAL, &gpll_init_cfg);
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/*
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* select apll as cpu/core clock pll source and
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* set up dependent divisors for PERI and ACLK clocks.
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* core hz : apll = 1:1
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*/
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aclk_div = APLL_HZ / CORE_ACLK_HZ - 1;
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assert((aclk_div + 1) * CORE_ACLK_HZ == APLL_HZ && aclk_div < 0x7);
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pclk_div = APLL_HZ / CORE_PERI_HZ - 1;
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assert((pclk_div + 1) * CORE_PERI_HZ == APLL_HZ && pclk_div < 0xf);
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rk_clrsetreg(&cru->cru_clksel_con[0],
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CORE_CLK_PLL_SEL_MASK | CORE_DIV_CON_MASK,
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CORE_CLK_PLL_SEL_APLL << CORE_CLK_PLL_SEL_SHIFT |
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0 << CORE_DIV_CON_SHIFT);
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rk_clrsetreg(&cru->cru_clksel_con[1],
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CORE_ACLK_DIV_MASK | CORE_PERI_DIV_MASK,
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aclk_div << CORE_ACLK_DIV_SHIFT |
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pclk_div << CORE_PERI_DIV_SHIFT);
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/*
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* select apll as pd_bus bus clock source and
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* set up dependent divisors for PCLK/HCLK and ACLK clocks.
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*/
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aclk_div = GPLL_HZ / BUS_ACLK_HZ - 1;
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assert((aclk_div + 1) * BUS_ACLK_HZ == GPLL_HZ && aclk_div <= 0x1f);
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pclk_div = GPLL_HZ / BUS_PCLK_HZ - 1;
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assert((pclk_div + 1) * BUS_PCLK_HZ == GPLL_HZ && pclk_div <= 0x7);
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hclk_div = GPLL_HZ / BUS_HCLK_HZ - 1;
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assert((hclk_div + 1) * BUS_HCLK_HZ == GPLL_HZ && hclk_div <= 0x3);
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rk_clrsetreg(&cru->cru_clksel_con[0],
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BUS_ACLK_PLL_SEL_MASK | BUS_ACLK_DIV_MASK,
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BUS_ACLK_PLL_SEL_GPLL << BUS_ACLK_PLL_SEL_SHIFT |
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aclk_div << BUS_ACLK_DIV_SHIFT);
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rk_clrsetreg(&cru->cru_clksel_con[1],
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BUS_PCLK_DIV_MASK | BUS_HCLK_DIV_MASK,
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pclk_div << BUS_PCLK_DIV_SHIFT |
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hclk_div << BUS_HCLK_DIV_SHIFT);
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/*
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* select gpll as pd_peri bus clock source and
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* set up dependent divisors for PCLK/HCLK and ACLK clocks.
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*/
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aclk_div = GPLL_HZ / PERI_ACLK_HZ - 1;
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assert((aclk_div + 1) * PERI_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f);
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hclk_div = ilog2(PERI_ACLK_HZ / PERI_HCLK_HZ);
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assert((1 << hclk_div) * PERI_HCLK_HZ ==
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PERI_ACLK_HZ && (hclk_div < 0x4));
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pclk_div = ilog2(PERI_ACLK_HZ / PERI_PCLK_HZ);
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assert((1 << pclk_div) * PERI_PCLK_HZ ==
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PERI_ACLK_HZ && pclk_div < 0x8);
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rk_clrsetreg(&cru->cru_clksel_con[10],
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PERI_PLL_SEL_MASK | PERI_PCLK_DIV_MASK |
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PERI_HCLK_DIV_MASK | PERI_ACLK_DIV_MASK,
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PERI_PLL_GPLL << PERI_PLL_SEL_SHIFT |
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pclk_div << PERI_PCLK_DIV_SHIFT |
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hclk_div << PERI_HCLK_DIV_SHIFT |
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aclk_div << PERI_ACLK_DIV_SHIFT);
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/* PLL enter normal-mode */
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rk_clrsetreg(&cru->cru_mode_con,
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GPLL_MODE_MASK | APLL_MODE_MASK,
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GPLL_MODE_NORM << GPLL_MODE_SHIFT |
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APLL_MODE_NORM << APLL_MODE_SHIFT);
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}
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/* Get pll rate by id */
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static uint32_t rkclk_pll_get_rate(struct rk3036_cru *cru,
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enum rk_clk_id clk_id)
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{
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uint32_t refdiv, fbdiv, postdiv1, postdiv2;
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uint32_t con;
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int pll_id = rk_pll_id(clk_id);
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struct rk3036_pll *pll = &cru->pll[pll_id];
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static u8 clk_shift[CLK_COUNT] = {
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0xff, APLL_MODE_SHIFT, DPLL_MODE_SHIFT, 0xff,
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GPLL_MODE_SHIFT, 0xff
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};
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static u32 clk_mask[CLK_COUNT] = {
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0xffffffff, APLL_MODE_MASK, DPLL_MODE_MASK, 0xffffffff,
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GPLL_MODE_MASK, 0xffffffff
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};
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uint shift;
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uint mask;
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con = readl(&cru->cru_mode_con);
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shift = clk_shift[clk_id];
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mask = clk_mask[clk_id];
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switch ((con & mask) >> shift) {
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case GPLL_MODE_SLOW:
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return OSC_HZ;
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case GPLL_MODE_NORM:
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/* normal mode */
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con = readl(&pll->con0);
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postdiv1 = (con & PLL_POSTDIV1_MASK) >> PLL_POSTDIV1_SHIFT;
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fbdiv = (con & PLL_FBDIV_MASK) >> PLL_FBDIV_SHIFT;
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con = readl(&pll->con1);
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postdiv2 = (con & PLL_POSTDIV2_MASK) >> PLL_POSTDIV2_SHIFT;
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refdiv = (con & PLL_REFDIV_MASK) >> PLL_REFDIV_SHIFT;
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return (24 * fbdiv / (refdiv * postdiv1 * postdiv2)) * 1000000;
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case GPLL_MODE_DEEP:
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default:
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return 32768;
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}
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}
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static ulong rockchip_mmc_get_clk(struct rk3036_cru *cru, uint clk_general_rate,
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int periph)
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{
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uint src_rate;
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uint div, mux;
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u32 con;
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switch (periph) {
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case HCLK_EMMC:
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case SCLK_EMMC:
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con = readl(&cru->cru_clksel_con[12]);
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mux = (con & EMMC_PLL_MASK) >> EMMC_PLL_SHIFT;
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div = (con & EMMC_DIV_MASK) >> EMMC_DIV_SHIFT;
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break;
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case HCLK_SDIO:
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case SCLK_SDIO:
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con = readl(&cru->cru_clksel_con[12]);
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mux = (con & MMC0_PLL_MASK) >> MMC0_PLL_SHIFT;
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div = (con & MMC0_DIV_MASK) >> MMC0_DIV_SHIFT;
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break;
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default:
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return -EINVAL;
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}
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src_rate = mux == EMMC_SEL_24M ? OSC_HZ : clk_general_rate;
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return DIV_TO_RATE(src_rate, div) / 2;
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}
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static ulong rockchip_mmc_set_clk(struct rk3036_cru *cru, uint clk_general_rate,
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int periph, uint freq)
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{
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int src_clk_div;
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int mux;
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debug("%s: clk_general_rate=%u\n", __func__, clk_general_rate);
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/* mmc clock auto divide 2 in internal */
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src_clk_div = DIV_ROUND_UP(clk_general_rate / 2, freq);
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if (src_clk_div > 128) {
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src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, freq);
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assert(src_clk_div - 1 < 128);
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mux = EMMC_SEL_24M;
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} else {
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mux = EMMC_SEL_GPLL;
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}
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switch (periph) {
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case HCLK_EMMC:
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case SCLK_EMMC:
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rk_clrsetreg(&cru->cru_clksel_con[12],
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EMMC_PLL_MASK | EMMC_DIV_MASK,
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mux << EMMC_PLL_SHIFT |
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(src_clk_div - 1) << EMMC_DIV_SHIFT);
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break;
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case HCLK_SDIO:
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case SCLK_SDIO:
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rk_clrsetreg(&cru->cru_clksel_con[11],
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MMC0_PLL_MASK | MMC0_DIV_MASK,
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mux << MMC0_PLL_SHIFT |
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(src_clk_div - 1) << MMC0_DIV_SHIFT);
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break;
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default:
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return -EINVAL;
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}
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return rockchip_mmc_get_clk(cru, clk_general_rate, periph);
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}
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static ulong rk3036_clk_get_rate(struct clk *clk)
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{
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struct rk3036_clk_priv *priv = dev_get_priv(clk->dev);
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switch (clk->id) {
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case 0 ... 63:
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return rkclk_pll_get_rate(priv->cru, clk->id);
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default:
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return -ENOENT;
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}
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}
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static ulong rk3036_clk_set_rate(struct clk *clk, ulong rate)
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{
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struct rk3036_clk_priv *priv = dev_get_priv(clk->dev);
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ulong new_rate, gclk_rate;
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gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL);
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switch (clk->id) {
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case 0 ... 63:
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return 0;
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case HCLK_EMMC:
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case SCLK_EMMC:
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new_rate = rockchip_mmc_set_clk(priv->cru, gclk_rate,
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clk->id, rate);
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break;
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default:
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return -ENOENT;
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}
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return new_rate;
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}
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static struct clk_ops rk3036_clk_ops = {
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.get_rate = rk3036_clk_get_rate,
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.set_rate = rk3036_clk_set_rate,
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};
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static int rk3036_clk_ofdata_to_platdata(struct udevice *dev)
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{
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struct rk3036_clk_priv *priv = dev_get_priv(dev);
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priv->cru = dev_read_addr_ptr(dev);
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return 0;
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}
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static int rk3036_clk_probe(struct udevice *dev)
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{
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struct rk3036_clk_priv *priv = dev_get_priv(dev);
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rkclk_init(priv->cru);
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return 0;
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}
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static int rk3036_clk_bind(struct udevice *dev)
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{
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int ret;
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struct udevice *sys_child;
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struct sysreset_reg *priv;
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/* The reset driver does not have a device node, so bind it here */
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ret = device_bind_driver(dev, "rockchip_sysreset", "sysreset",
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&sys_child);
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if (ret) {
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debug("Warning: No sysreset driver: ret=%d\n", ret);
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} else {
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priv = malloc(sizeof(struct sysreset_reg));
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priv->glb_srst_fst_value = offsetof(struct rk3036_cru,
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cru_glb_srst_fst_value);
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priv->glb_srst_snd_value = offsetof(struct rk3036_cru,
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cru_glb_srst_snd_value);
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sys_child->priv = priv;
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}
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#if CONFIG_IS_ENABLED(CONFIG_RESET_ROCKCHIP)
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ret = offsetof(struct rk3036_cru, cru_softrst_con[0]);
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ret = rockchip_reset_bind(dev, ret, 9);
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if (ret)
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debug("Warning: software reset driver bind faile\n");
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#endif
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return 0;
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}
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static const struct udevice_id rk3036_clk_ids[] = {
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{ .compatible = "rockchip,rk3036-cru" },
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{ }
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};
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U_BOOT_DRIVER(rockchip_rk3036_cru) = {
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.name = "clk_rk3036",
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.id = UCLASS_CLK,
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.of_match = rk3036_clk_ids,
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.priv_auto_alloc_size = sizeof(struct rk3036_clk_priv),
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.ofdata_to_platdata = rk3036_clk_ofdata_to_platdata,
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.ops = &rk3036_clk_ops,
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.bind = rk3036_clk_bind,
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.probe = rk3036_clk_probe,
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};
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