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https://github.com/brain-hackers/u-boot-brain
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f45e747d6d
Newer Intel SoCs have different ways of setting up cache-as-ram (CAR). Add support for these along with suitable configuration options. To make the code cleaner, adjust a few definitions in processor.h so that they can be used from assembler. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
88 lines
1.6 KiB
ArmAsm
88 lines
1.6 KiB
ArmAsm
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright 2017 Intel Corp.
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* Copyright 2019 Google LLC
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* Taken from coreboot file exit_car.S
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*/
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#include <config.h>
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#include <asm/msr-index.h>
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#include <asm/mtrr.h>
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.text
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.global car_uninit
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car_uninit:
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/*
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* Retrieve return address from stack as it will get trashed below if
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* execution is utilizing the cache-as-ram stack.
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*/
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pop %ebx
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/* Disable MTRRs */
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mov $(MTRR_DEF_TYPE_MSR), %ecx
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rdmsr
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and $(~(MTRR_DEF_TYPE_EN | MTRR_DEF_TYPE_FIX_EN)), %eax
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wrmsr
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#ifdef CONFIG_INTEL_CAR_NEM
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.global car_nem_teardown
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car_nem_teardown:
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/* invalidate cache contents */
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invd
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/* Knock down bit 1 then bit 0 of NEM control not combining steps */
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mov $(MSR_EVICT_CTL), %ecx
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rdmsr
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and $(~(1 << 1)), %eax
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wrmsr
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and $(~(1 << 0)), %eax
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wrmsr
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#elif IS_ENABLED(CONFIG_INTEL_CAR_CQOS)
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.global car_cqos_teardown
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car_cqos_teardown:
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/* Go back to all-evicting mode, set both masks to all-1s */
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mov $MSR_L2_QOS_MASK(0), %ecx
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rdmsr
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mov $~0, %al
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wrmsr
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mov $MSR_L2_QOS_MASK(1), %ecx
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rdmsr
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mov $~0, %al
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wrmsr
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/* Reset CLOS selector to 0 */
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mov $MSR_IA32_PQR_ASSOC, %ecx
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rdmsr
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and $~MSR_IA32_PQR_ASSOC_MASK, %edx
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wrmsr
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#elif IS_ENABLED(CONFIG_INTEL_CAR_NEM_ENHANCED)
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.global car_nem_enhanced_teardown
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car_nem_enhanced_teardown:
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/* invalidate cache contents */
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invd
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/* Knock down bit 1 then bit 0 of NEM control not combining steps */
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mov $(MSR_EVICT_CTL), %ecx
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rdmsr
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and $(~(1 << 1)), %eax
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wrmsr
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and $(~(1 << 0)), %eax
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wrmsr
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/* Reset CLOS selector to 0 */
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mov $IA32_PQR_ASSOC, %ecx
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rdmsr
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and $~IA32_PQR_ASSOC_MASK, %edx
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wrmsr
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#endif
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/* Return to caller */
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jmp *%ebx
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