mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-18 07:58:52 +09:00
ea2e142843
This patch adds the CONFIG_4xx_DCACHE options to some SDRAM init files and to the Sequoia TLB init code. Now the cache can be enabled on 44x boards by defining CONFIG_4xx_DCACHE in the board config file. This option will disappear, when more boards use is successfully and no more known problems exist. This is tested successfully on Sequoia and Katmai. The only problem that needs to be fixed is, that USB is not working on Sequoia right now, since it will need some cache handling code too, similar to the 4xx EMAC driver. Signed-off-by: Stefan Roese <sr@denx.de>
165 lines
5.0 KiB
ArmAsm
165 lines
5.0 KiB
ArmAsm
/*
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <ppc_asm.tmpl>
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#include <config.h>
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/* General */
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#define TLB_VALID 0x00000200
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#define _256M 0x10000000
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/* Supported page sizes */
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#define SZ_1K 0x00000000
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#define SZ_4K 0x00000010
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#define SZ_16K 0x00000020
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#define SZ_64K 0x00000030
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#define SZ_256K 0x00000040
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#define SZ_1M 0x00000050
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#define SZ_8M 0x00000060
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#define SZ_16M 0x00000070
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#define SZ_256M 0x00000090
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/* Storage attributes */
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#define SA_W 0x00000800 /* Write-through */
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#define SA_I 0x00000400 /* Caching inhibited */
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#define SA_M 0x00000200 /* Memory coherence */
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#define SA_G 0x00000100 /* Guarded */
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#define SA_E 0x00000080 /* Endian */
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/* Access control */
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#define AC_X 0x00000024 /* Execute */
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#define AC_W 0x00000012 /* Write */
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#define AC_R 0x00000009 /* Read */
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/* Some handy macros */
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#define EPN(e) ((e) & 0xfffffc00)
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#define TLB0(epn,sz) ( (EPN((epn)) | (sz) | TLB_VALID ) )
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#define TLB1(rpn,erpn) ( ((rpn)&0xfffffc00) | (erpn) )
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#define TLB2(a) ( (a)&0x00000fbf )
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#define tlbtab_start\
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mflr r1 ;\
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bl 0f ;
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#define tlbtab_end\
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.long 0, 0, 0 ; \
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0: mflr r0 ; \
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mtlr r1 ; \
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blr ;
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#define tlbentry(epn,sz,rpn,erpn,attr)\
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.long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr)
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/**************************************************************************
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* TLB TABLE
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*
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* This table is used by the cpu boot code to setup the initial tlb
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* entries. Rather than make broad assumptions in the cpu source tree,
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* this table lets each board set things up however they like.
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*
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* Pointer to the table is returned in r1
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*
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*************************************************************************/
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.section .bootpg,"ax"
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.globl tlbtab
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tlbtab:
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tlbtab_start
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/*
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* BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
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* speed up boot process. It is patched after relocation to enable SA_I
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*/
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#ifndef CONFIG_NAND_SPL
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tlbentry( CFG_BOOT_BASE_ADDR, SZ_256M, CFG_BOOT_BASE_ADDR, 1, AC_R|AC_W|AC_X|SA_G )
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#else
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tlbentry( CFG_NAND_BOOT_SPL_SRC, SZ_4K, CFG_NAND_BOOT_SPL_SRC, 1, AC_R|AC_W|AC_X|SA_G )
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#endif
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/* TLB-entry for DDR SDRAM (Up to 2GB) */
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#ifdef CONFIG_4xx_DCACHE
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tlbentry( CFG_SDRAM_BASE, SZ_256M, CFG_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G)
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#else
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tlbentry( CFG_SDRAM_BASE, SZ_256M, CFG_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
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#endif
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#ifdef CFG_INIT_RAM_DCACHE
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/* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
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tlbentry( CFG_INIT_RAM_ADDR, SZ_64K, CFG_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G )
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#endif
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/* TLB-entry for PCI Memory */
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tlbentry( CFG_PCI_MEMBASE, SZ_256M, CFG_PCI_MEMBASE, 1, AC_R|AC_W|SA_G|SA_I )
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tlbentry( CFG_PCI_MEMBASE1, SZ_256M, CFG_PCI_MEMBASE1, 1, AC_R|AC_W|SA_G|SA_I )
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tlbentry( CFG_PCI_MEMBASE2, SZ_256M, CFG_PCI_MEMBASE2, 1, AC_R|AC_W|SA_G|SA_I )
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tlbentry( CFG_PCI_MEMBASE3, SZ_256M, CFG_PCI_MEMBASE3, 1, AC_R|AC_W|SA_G|SA_I )
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/* TLB-entry for EBC */
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tlbentry( CFG_BCSR_BASE, SZ_1K, CFG_BCSR_BASE, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
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/* TLB-entry for NAND */
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tlbentry( CFG_NAND_ADDR, SZ_1K, CFG_NAND_ADDR, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
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/* TLB-entry for Internal Registers & OCM */
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tlbentry( 0xe0000000, SZ_16M, 0xe0000000, 0, AC_R|AC_W|AC_X|SA_I )
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/*TLB-entry PCI registers*/
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tlbentry( 0xEEC00000, SZ_1K, 0xEEC00000, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
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/* TLB-entry for peripherals */
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tlbentry( 0xEF000000, SZ_16M, 0xEF000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
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/* TLB-entry PCI IO Space - from sr@denx.de */
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tlbentry(0xE8000000, SZ_64K, 0xE8000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
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tlbtab_end
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#if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
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/*
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* For NAND booting the first TLB has to be reconfigured to full size
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* and with caching disabled after running from RAM!
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*/
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#define TLB00 TLB0(CFG_BOOT_BASE_ADDR, SZ_256M)
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#define TLB01 TLB1(CFG_BOOT_BASE_ADDR, 1)
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#define TLB02 TLB2(AC_R|AC_W|AC_X|SA_G|SA_I)
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.globl reconfig_tlb0
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reconfig_tlb0:
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sync
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isync
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addi r4,r0,0x0000 /* TLB entry #0 */
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lis r5,TLB00@h
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ori r5,r5,TLB00@l
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tlbwe r5,r4,0x0000 /* Save it out */
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lis r5,TLB01@h
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ori r5,r5,TLB01@l
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tlbwe r5,r4,0x0001 /* Save it out */
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lis r5,TLB02@h
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ori r5,r5,TLB02@l
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tlbwe r5,r4,0x0002 /* Save it out */
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sync
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isync
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blr
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#endif
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