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https://github.com/brain-hackers/u-boot-brain
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b5e01eecc8
GP EVM has 1GB DDR3 attached(Part no: MT41K512M8RH). Adding details for the same. Below is the brief description of DDR3 init sequence(SW leveling): -> Enable VTT regulator -> Configure VTP -> Configure DDR IO settings -> Disable initialization and refreshes until EMIF registers are programmed. -> Program Timing registers -> Program leveling registers -> Program PHY control and Temp alert and ZQ config registers. -> Enable initialization and refreshes and configure SDRAM CONFIG register Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
29 lines
682 B
C
29 lines
682 B
C
/*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _GPIO_AM33xx_H
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#define _GPIO_AM33xx_H
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#include <asm/omap_gpio.h>
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#define OMAP_MAX_GPIO 128
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#define AM33XX_GPIO0_BASE 0x44E07000
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#define AM33XX_GPIO1_BASE 0x4804C000
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#define AM33XX_GPIO2_BASE 0x481AC000
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#define AM33XX_GPIO3_BASE 0x481AE000
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#define GPIO_22 22
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/* GPIO CTRL register */
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#define GPIO_CTRL_DISABLEMODULE_SHIFT 0
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#define GPIO_CTRL_DISABLEMODULE_MASK (1 << 0)
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#define GPIO_CTRL_ENABLEMODULE GPIO_CTRL_DISABLEMODULE_MASK
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/* GPIO OUTPUT ENABLE register */
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#define GPIO_OE_ENABLE(x) (1 << x)
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/* GPIO SETDATAOUT register */
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#define GPIO_SETDATAOUT(x) (1 << x)
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#endif /* _GPIO_AM33xx_H */
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