mirror of
https://github.com/brain-hackers/u-boot-brain
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3d54eabcaf
The SPL binary needs to be prefixed with the boot magic ('RK33' for
the RK3399) on the Rockchip platform and starts execution of the
instruction word following immediately after this boot magic.
This poses a challenge for AArch64 (ARMv8) binaries, as the .text
section would need to start on the odd address, violating natural
alignment (and potentially triggering a fault for any code that
tries to access 64bit values embedded in the .text section).
A quick and easy fix is to have the .text section include the 'RK33'
magic and pad it with a boot0 hook to insert 4 bytes of padding at the
start of the section (with the intention of having mkimage overwrite
this padding with the appropriate boot magic). This avoids having to
modify the linker scripts or more complex logic in mkimage.
X-AffectedPlatforms: RK3399-Q7
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Tested-by: Klaus Goger <klaus.goger@theobroma-systems.com>
89 lines
2.2 KiB
C
89 lines
2.2 KiB
C
/*
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* (C) Copyright 2016 Rockchip Electronics Co., Ltd
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __CONFIG_RK3399_COMMON_H
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#define __CONFIG_RK3399_COMMON_H
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#include "rockchip-common.h"
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#define CONFIG_NR_DRAM_BANKS 1
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#define CONFIG_ENV_SIZE 0x2000
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#define CONFIG_SYS_MAXARGS 16
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#define CONFIG_SYS_MALLOC_LEN (32 << 20)
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#define CONFIG_SYS_CBSIZE 1024
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#define CONFIG_SKIP_LOWLEVEL_INIT
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#define CONFIG_SPL_FRAMEWORK
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#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
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#define CONFIG_SPL_LIBCOMMON_SUPPORT
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#define CONFIG_SPL_LIBGENERIC_SUPPORT
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#define CONFIG_SPL_SERIAL_SUPPORT
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#define CONFIG_SYS_NS16550_MEM32
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#define CONFIG_SYS_TEXT_BASE 0x00200000
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#define CONFIG_SYS_INIT_SP_ADDR 0x00300000
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#define CONFIG_SYS_LOAD_ADDR 0x00800800
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#define CONFIG_SPL_STACK 0xff8effff
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#define CONFIG_SPL_TEXT_BASE 0xff8c2000
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#define CONFIG_SPL_MAX_SIZE 0x30000
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/* BSS setup */
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#define CONFIG_SPL_BSS_START_ADDR 0xff8e0000
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#define CONFIG_SPL_BSS_MAX_SIZE 0x10000
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#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */
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/* MMC/SD IP block */
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#define CONFIG_BOUNCE_BUFFER
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#define CONFIG_ROCKCHIP_SDHCI_MAX_FREQ 200000000
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#define CONFIG_SUPPORT_VFAT
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#define CONFIG_FS_FAT
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#define CONFIG_FAT_WRITE
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#define CONFIG_FS_EXT4
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/* RAW SD card / eMMC locations. */
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#define CONFIG_SYS_SPI_U_BOOT_OFFS (128 << 10)
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/* FAT sd card locations. */
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#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
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#define CONFIG_SYS_SDRAM_BASE 0
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#define CONFIG_NR_DRAM_BANKS 1
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#define CONFIG_SPI_FLASH
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#define CONFIG_SPI
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#define CONFIG_SF_DEFAULT_SPEED 20000000
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#ifndef CONFIG_SPL_BUILD
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#define ENV_MEM_LAYOUT_SETTINGS \
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"scriptaddr=0x00000000\0" \
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"pxefile_addr_r=0x00100000\0" \
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"fdt_addr_r=0x01f00000\0" \
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"kernel_addr_r=0x02000000\0" \
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"ramdisk_addr_r=0x04000000\0"
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#include <config_distro_bootcmd.h>
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#define CONFIG_EXTRA_ENV_SETTINGS \
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ENV_MEM_LAYOUT_SETTINGS \
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"partitions=" PARTS_DEFAULT \
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BOOTENV
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#endif
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/* enable usb config for usb ether */
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#define CONFIG_USB_HOST_ETHER
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#define CONFIG_USB_ETHER_ASIX
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#define CONFIG_USB_ETHER_ASIX88179
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#define CONFIG_USB_ETHER_MCS7830
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#define CONFIG_USB_ETHER_SMSC95XX
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#define CONFIG_USB_ETHER_RTL8152
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/* rockchip xhci host driver */
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#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
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#endif
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