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https://github.com/brain-hackers/u-boot-brain
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1a4596601f
Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com>
62 lines
1016 B
ArmAsm
62 lines
1016 B
ArmAsm
/*
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* Copyright (C) 2000 Murray Jensen <Murray.Jensen@cmst.csiro.au>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <config.h>
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#include <command.h>
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#include <74xx_7xx.h>
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#include <version.h>
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#include <ppc_asm.tmpl>
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#include <ppc_defs.h>
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#include <asm/cache.h>
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#include <asm/mmu.h>
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#if defined(CONFIG_CMD_KGDB)
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/*
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* cache flushing routines for kgdb
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*/
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.globl kgdb_flush_cache_all
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kgdb_flush_cache_all:
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lis r3,0
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addis r4,r0,0x0040
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kgdb_flush_loop:
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lwz r5,0(r3)
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addi r3,r3,CONFIG_SYS_CACHELINE_SIZE
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cmp 0,0,r3,r4
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bne kgdb_flush_loop
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SYNC
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mfspr r3,1008
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ori r3,r3,0x8800
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mtspr 1008,r3
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sync
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blr
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.globl kgdb_flush_cache_range
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kgdb_flush_cache_range:
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li r5,CONFIG_SYS_CACHELINE_SIZE-1
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andc r3,r3,r5
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subf r4,r3,r4
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add r4,r4,r5
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srwi. r4,r4,CONFIG_SYS_CACHELINE_SHIFT
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beqlr
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mtctr r4
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mr r6,r3
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1: dcbst 0,r3
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addi r3,r3,CONFIG_SYS_CACHELINE_SIZE
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bdnz 1b
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sync /* wait for dcbst's to get to ram */
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mtctr r4
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2: icbi 0,r6
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addi r6,r6,CONFIG_SYS_CACHELINE_SIZE
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bdnz 2b
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SYNC
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blr
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#endif
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