mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-09-07 05:13:21 +09:00
d024236e5a
We have a large number of places where while we historically referenced gd in the code we no longer do, as well as cases where the code added that line "just in case" during development and never dropped it. Signed-off-by: Tom Rini <trini@konsulko.com>
100 lines
2.2 KiB
C
100 lines
2.2 KiB
C
/*
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* (C) Copyright 2017 Rockchip Electronics Co., Ltd
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <debug_uart.h>
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#include <dm.h>
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#include <ram.h>
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#include <spl.h>
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#include <asm/io.h>
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#include <asm/arch/bootrom.h>
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#include <asm/arch/cru_rk322x.h>
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#include <asm/arch/grf_rk322x.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/timer.h>
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#include <asm/arch/uart.h>
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u32 spl_boot_device(void)
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{
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return BOOT_DEVICE_MMC1;
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}
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#define GRF_BASE 0x11000000
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#define SGRF_BASE 0x10140000
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#define DEBUG_UART_BASE 0x11030000
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void board_debug_uart_init(void)
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{
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static struct rk322x_grf * const grf = (void *)GRF_BASE;
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enum {
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GPIO1B2_SHIFT = 4,
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GPIO1B2_MASK = 3 << GPIO1B2_SHIFT,
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GPIO1B2_GPIO = 0,
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GPIO1B2_UART1_SIN,
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GPIO1B2_UART21_SIN,
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GPIO1B1_SHIFT = 2,
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GPIO1B1_MASK = 3 << GPIO1B1_SHIFT,
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GPIO1B1_GPIO = 0,
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GPIO1B1_UART1_SOUT,
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GPIO1B1_UART21_SOUT,
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};
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enum {
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CON_IOMUX_UART2SEL_SHIFT= 8,
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CON_IOMUX_UART2SEL_MASK = 1 << CON_IOMUX_UART2SEL_SHIFT,
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CON_IOMUX_UART2SEL_2 = 0,
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CON_IOMUX_UART2SEL_21,
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};
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/* Enable early UART2 channel 1 on the RK322x */
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rk_clrsetreg(&grf->gpio1b_iomux,
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GPIO1B1_MASK | GPIO1B2_MASK,
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GPIO1B2_UART21_SIN << GPIO1B2_SHIFT |
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GPIO1B1_UART21_SOUT << GPIO1B1_SHIFT);
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/* Set channel C as UART2 input */
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rk_clrsetreg(&grf->con_iomux,
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CON_IOMUX_UART2SEL_MASK,
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CON_IOMUX_UART2SEL_21 << CON_IOMUX_UART2SEL_SHIFT);
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}
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#define SGRF_DDR_CON0 0x10150000
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void board_init_f(ulong dummy)
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{
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struct udevice *dev;
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int ret;
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/*
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* Debug UART can be used from here if required:
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*
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* debug_uart_init();
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* printch('a');
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* printhex8(0x1234);
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* printascii("string");
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*/
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debug_uart_init();
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printascii("SPL Init");
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ret = spl_early_init();
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if (ret) {
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debug("spl_early_init() failed: %d\n", ret);
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hang();
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}
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rockchip_timer_init();
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printf("timer init done\n");
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ret = uclass_get_device(UCLASS_RAM, 0, &dev);
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if (ret) {
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printf("DRAM init failed: %d\n", ret);
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return;
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}
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/* Disable the ddr secure region setting to make it non-secure */
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rk_clrreg(SGRF_DDR_CON0, 0x4000);
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#if defined(CONFIG_SPL_ROCKCHIP_BACK_TO_BROM) && !defined(CONFIG_SPL_BOARD_INIT)
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back_to_bootrom(BROM_BOOT_NEXTSTAGE);
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#endif
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}
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