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![Pramod Kumar](/assets/img/avatar_default.png)
Current implementation to get board version through GPIO is broken due to endianness issue hence it is not working for rev B board. Fix it to make it work for Rev A as well as Rev B boards Signed-off-by: Pramod Kumar <pramod.kumar_1@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
229 lines
5.1 KiB
C
229 lines
5.1 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2019 NXP
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*/
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#include <common.h>
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#include <i2c.h>
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#include <fdt_support.h>
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/fsl_serdes.h>
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#include <asm/arch/soc.h>
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#include <asm/arch-fsl-layerscape/fsl_icid.h>
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#include <hwconfig.h>
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#include <ahci.h>
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#include <mmc.h>
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#include <scsi.h>
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#include <fm_eth.h>
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#include <fsl_csu.h>
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#include <fsl_esdhc.h>
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#include <fsl_sec.h>
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#include <fsl_dspi.h>
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#define LS1046A_PORSR1_REG 0x1EE0000
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#define BOOT_SRC_SD 0x20000000
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#define BOOT_SRC_MASK 0xFF800000
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#define BOARD_REV_GPIO_SHIFT 17
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#define BOARD_REV_MASK 0x03
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#define USB2_SEL_MASK 0x00000100
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#define BYTE_SWAP_32(word) ((((word) & 0xff000000) >> 24) | \
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(((word) & 0x00ff0000) >> 8) | \
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(((word) & 0x0000ff00) << 8) | \
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(((word) & 0x000000ff) << 24))
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#define SPI_MCR_REG 0x2100000
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DECLARE_GLOBAL_DATA_PTR;
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int select_i2c_ch_pca9547(u8 ch)
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{
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int ret;
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ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
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if (ret) {
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puts("PCA: failed to select proper channel\n");
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return ret;
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}
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return 0;
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}
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static inline void demux_select_usb2(void)
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{
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u32 val;
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struct ccsr_gpio *pgpio = (void *)(GPIO3_BASE_ADDR);
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val = in_be32(&pgpio->gpdir);
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val |= USB2_SEL_MASK;
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out_be32(&pgpio->gpdir, val);
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val = in_be32(&pgpio->gpdat);
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val |= USB2_SEL_MASK;
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out_be32(&pgpio->gpdat, val);
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}
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static inline void set_spi_cs_signal_inactive(void)
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{
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/* default: all CS signals inactive state is high */
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uint mcr_val;
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uint mcr_cfg_val = DSPI_MCR_MSTR | DSPI_MCR_PCSIS_MASK |
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DSPI_MCR_CRXF | DSPI_MCR_CTXF;
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mcr_val = in_be32(SPI_MCR_REG);
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mcr_val |= DSPI_MCR_HALT;
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out_be32(SPI_MCR_REG, mcr_val);
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out_be32(SPI_MCR_REG, mcr_cfg_val);
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mcr_val = in_be32(SPI_MCR_REG);
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mcr_val &= ~DSPI_MCR_HALT;
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out_be32(SPI_MCR_REG, mcr_val);
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}
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int board_early_init_f(void)
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{
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fsl_lsch2_early_init_f();
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return 0;
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}
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static inline uint8_t get_board_version(void)
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{
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struct ccsr_gpio *pgpio = (void *)(GPIO2_BASE_ADDR);
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/* GPIO 13 and GPIO 14 are used for Board Rev */
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u32 gpio_val = ((in_be32(&pgpio->gpdat) >> BOARD_REV_GPIO_SHIFT))
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& BOARD_REV_MASK;
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/* GPIOs' are 0..31 in Big Endiness, swap GPIO 13 and GPIO 14 */
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u8 val = ((gpio_val >> 1) | (gpio_val << 1)) & BOARD_REV_MASK;
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return val;
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}
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int checkboard(void)
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{
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static const char *freq[2] = {"100.00MHZ", "100.00MHZ"};
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u32 boot_src;
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u8 rev;
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rev = get_board_version();
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switch (rev) {
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case 0x00:
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puts("Board: LS1046AFRWY, Rev: A, boot from ");
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break;
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case 0x01:
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puts("Board: LS1046AFRWY, Rev: B, boot from ");
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break;
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default:
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puts("Board: LS1046AFRWY, Rev: Unknown, boot from ");
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break;
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}
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boot_src = BYTE_SWAP_32(readl(LS1046A_PORSR1_REG));
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if ((boot_src & BOOT_SRC_MASK) == BOOT_SRC_SD)
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puts("SD\n");
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else
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puts("QSPI\n");
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printf("SD1_CLK1 = %s, SD1_CLK2 = %s\n", freq[0], freq[1]);
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return 0;
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}
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int board_init(void)
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{
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#ifdef CONFIG_NXP_ESBC
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/*
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* In case of Secure Boot, the IBR configures the SMMU
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* to allow only Secure transactions.
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* SMMU must be reset in bypass mode.
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* Set the ClientPD bit and Clear the USFCFG Bit
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*/
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u32 val;
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val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
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out_le32(SMMU_SCR0, val);
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val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
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out_le32(SMMU_NSCR0, val);
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#endif
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#ifdef CONFIG_FSL_CAAM
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sec_init();
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#endif
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select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
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return 0;
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}
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int board_setup_core_volt(u32 vdd)
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{
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return 0;
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}
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void config_board_mux(void)
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{
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#ifdef CONFIG_HAS_FSL_XHCI_USB
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struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
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u32 usb_pwrfault;
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/*
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* USB2 is used, configure mux to USB2_DRVVBUS/USB2_PWRFAULT
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* USB3 is not used, configure mux to IIC4_SCL/IIC4_SDA
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*/
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out_be32(&scfg->rcwpmuxcr0, 0x3300);
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#ifdef CONFIG_HAS_FSL_IIC3
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/* IIC3 is used, configure mux to use IIC3_SCL/IIC3/SDA */
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out_be32(&scfg->rcwpmuxcr0, 0x0000);
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#endif
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out_be32(&scfg->usbdrvvbus_selcr, SCFG_USBDRVVBUS_SELCR_USB1);
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usb_pwrfault = (SCFG_USBPWRFAULT_DEDICATED <<
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SCFG_USBPWRFAULT_USB3_SHIFT) |
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(SCFG_USBPWRFAULT_DEDICATED <<
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SCFG_USBPWRFAULT_USB2_SHIFT) |
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(SCFG_USBPWRFAULT_SHARED <<
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SCFG_USBPWRFAULT_USB1_SHIFT);
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out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault);
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#ifndef CONFIG_HAS_FSL_IIC3
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/*
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* LS1046A FRWY board has demultiplexer NX3DV42GU with GPIO3_23 as input
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* to select I2C3_USB2_SEL_IO
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* I2C3_USB2_SEL = 0: I2C3_SCL/SDA signals are routed to
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* I2C3 header (default)
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* I2C3_USB2_SEL = 1: USB2_DRVVBUS/PWRFAULT signals are routed to
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* USB2 port
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* programmed to select USB2 by setting GPIO3_23 output to one
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*/
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demux_select_usb2();
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#endif
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#endif
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set_spi_cs_signal_inactive();
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}
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#ifdef CONFIG_MISC_INIT_R
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int misc_init_r(void)
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{
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config_board_mux();
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return 0;
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}
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#endif
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int ft_board_setup(void *blob, bd_t *bd)
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{
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u64 base[CONFIG_NR_DRAM_BANKS];
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u64 size[CONFIG_NR_DRAM_BANKS];
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/* fixup DT for the two DDR banks */
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base[0] = gd->bd->bi_dram[0].start;
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size[0] = gd->bd->bi_dram[0].size;
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base[1] = gd->bd->bi_dram[1].start;
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size[1] = gd->bd->bi_dram[1].size;
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fdt_fixup_memory_banks(blob, base, size, 2);
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ft_cpu_setup(blob, bd);
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#ifdef CONFIG_SYS_DPAA_FMAN
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fdt_fixup_fman_ethernet(blob);
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#endif
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fdt_fixup_icid(blob);
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return 0;
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}
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