mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
295 lines
7.2 KiB
C
295 lines
7.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* (C) Copyright 2010
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* Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
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*/
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#ifndef __GDSYS_FPGA_H
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#define __GDSYS_FPGA_H
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int init_func_fpga(void);
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enum {
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FPGA_STATE_DONE_FAILED = 1 << 0,
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FPGA_STATE_REFLECTION_FAILED = 1 << 1,
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FPGA_STATE_PLATFORM = 1 << 2,
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};
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int get_fpga_state(unsigned dev);
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int fpga_set_reg(u32 fpga, u16 *reg, off_t regoff, u16 data);
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int fpga_get_reg(u32 fpga, u16 *reg, off_t regoff, u16 *data);
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extern struct ihs_fpga *fpga_ptr[];
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#define FPGA_SET_REG(ix, fld, val) \
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fpga_set_reg((ix), \
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&fpga_ptr[ix]->fld, \
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offsetof(struct ihs_fpga, fld), \
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val)
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#define FPGA_GET_REG(ix, fld, val) \
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fpga_get_reg((ix), \
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&fpga_ptr[ix]->fld, \
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offsetof(struct ihs_fpga, fld), \
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val)
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struct ihs_gpio {
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u16 read;
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u16 clear;
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u16 set;
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};
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struct ihs_i2c {
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u16 interrupt_status;
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u16 interrupt_enable;
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u16 write_mailbox_ext;
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u16 write_mailbox;
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u16 read_mailbox_ext;
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u16 read_mailbox;
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};
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struct ihs_osd {
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u16 version;
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u16 features;
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u16 control;
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u16 xy_size;
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u16 xy_scale;
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u16 x_pos;
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u16 y_pos;
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};
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struct ihs_mdio {
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u16 control;
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u16 address_data;
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u16 rx_data;
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};
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struct ihs_io_ep {
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u16 transmit_data;
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u16 rx_tx_control;
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u16 receive_data;
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u16 rx_tx_status;
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u16 reserved;
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u16 device_address;
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u16 target_address;
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};
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#ifdef CONFIG_NEO
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struct ihs_fpga {
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u16 reflection_low; /* 0x0000 */
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u16 versions; /* 0x0002 */
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u16 fpga_features; /* 0x0004 */
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u16 fpga_version; /* 0x0006 */
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u16 reserved_0[8187]; /* 0x0008 */
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u16 reflection_high; /* 0x3ffe */
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};
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#endif
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#ifdef CONFIG_IO
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struct ihs_fpga {
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u16 reflection_low; /* 0x0000 */
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u16 versions; /* 0x0002 */
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u16 fpga_features; /* 0x0004 */
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u16 fpga_version; /* 0x0006 */
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u16 reserved_0[5]; /* 0x0008 */
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u16 quad_serdes_reset; /* 0x0012 */
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u16 reserved_1[8181]; /* 0x0014 */
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u16 reflection_high; /* 0x3ffe */
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};
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#endif
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#ifdef CONFIG_IO64
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struct ihs_fpga_channel {
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u16 status_int;
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u16 config_int;
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u16 switch_connect_config;
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u16 tx_destination;
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};
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struct ihs_fpga_hicb {
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u16 status_int;
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u16 config_int;
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};
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struct ihs_fpga {
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u16 reflection_low; /* 0x0000 */
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u16 versions; /* 0x0002 */
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u16 fpga_features; /* 0x0004 */
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u16 fpga_version; /* 0x0006 */
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u16 reserved_0[5]; /* 0x0008 */
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u16 quad_serdes_reset; /* 0x0012 */
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u16 reserved_1[502]; /* 0x0014 */
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struct ihs_fpga_channel ch[32]; /* 0x0400 */
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struct ihs_fpga_channel hicb_ch[32]; /* 0x0500 */
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u16 reserved_2[7487]; /* 0x0580 */
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u16 reflection_high; /* 0x3ffe */
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};
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#endif
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#ifdef CONFIG_IOCON
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struct ihs_fpga {
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u16 reflection_low; /* 0x0000 */
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u16 versions; /* 0x0002 */
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u16 fpga_version; /* 0x0004 */
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u16 fpga_features; /* 0x0006 */
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u16 reserved_0[1]; /* 0x0008 */
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u16 top_interrupt; /* 0x000a */
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u16 reserved_1[4]; /* 0x000c */
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struct ihs_gpio gpio; /* 0x0014 */
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u16 mpc3w_control; /* 0x001a */
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u16 reserved_2[2]; /* 0x001c */
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struct ihs_io_ep ep; /* 0x0020 */
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u16 reserved_3[9]; /* 0x002e */
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struct ihs_i2c i2c0; /* 0x0040 */
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u16 reserved_4[10]; /* 0x004c */
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u16 mc_int; /* 0x0060 */
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u16 mc_int_en; /* 0x0062 */
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u16 mc_status; /* 0x0064 */
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u16 mc_control; /* 0x0066 */
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u16 mc_tx_data; /* 0x0068 */
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u16 mc_tx_address; /* 0x006a */
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u16 mc_tx_cmd; /* 0x006c */
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u16 mc_res; /* 0x006e */
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u16 mc_rx_cmd_status; /* 0x0070 */
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u16 mc_rx_data; /* 0x0072 */
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u16 reserved_5[69]; /* 0x0074 */
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u16 reflection_high; /* 0x00fe */
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struct ihs_osd osd0; /* 0x0100 */
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u16 reserved_6[889]; /* 0x010e */
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u16 videomem0[2048]; /* 0x0800 */
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};
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#endif
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#if defined(CONFIG_HRCON) || defined(CONFIG_STRIDER_CON_DP)
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struct ihs_fpga {
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u16 reflection_low; /* 0x0000 */
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u16 versions; /* 0x0002 */
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u16 fpga_version; /* 0x0004 */
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u16 fpga_features; /* 0x0006 */
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u16 reserved_0[1]; /* 0x0008 */
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u16 top_interrupt; /* 0x000a */
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u16 reserved_1[2]; /* 0x000c */
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u16 control; /* 0x0010 */
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u16 extended_control; /* 0x0012 */
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struct ihs_gpio gpio; /* 0x0014 */
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u16 mpc3w_control; /* 0x001a */
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u16 reserved_2[2]; /* 0x001c */
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struct ihs_io_ep ep; /* 0x0020 */
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u16 reserved_3[9]; /* 0x002e */
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struct ihs_i2c i2c0; /* 0x0040 */
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u16 reserved_4[10]; /* 0x004c */
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u16 mc_int; /* 0x0060 */
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u16 mc_int_en; /* 0x0062 */
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u16 mc_status; /* 0x0064 */
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u16 mc_control; /* 0x0066 */
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u16 mc_tx_data; /* 0x0068 */
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u16 mc_tx_address; /* 0x006a */
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u16 mc_tx_cmd; /* 0x006c */
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u16 mc_res; /* 0x006e */
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u16 mc_rx_cmd_status; /* 0x0070 */
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u16 mc_rx_data; /* 0x0072 */
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u16 reserved_5[69]; /* 0x0074 */
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u16 reflection_high; /* 0x00fe */
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struct ihs_osd osd0; /* 0x0100 */
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#ifdef CONFIG_SYS_OSD_DH
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u16 reserved_6[57]; /* 0x010e */
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struct ihs_osd osd1; /* 0x0180 */
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u16 reserved_7[9]; /* 0x018e */
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struct ihs_i2c i2c1; /* 0x01a0 */
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u16 reserved_8[1834]; /* 0x01ac */
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u16 videomem0[2048]; /* 0x1000 */
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u16 videomem1[2048]; /* 0x2000 */
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#else
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u16 reserved_6[889]; /* 0x010e */
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u16 videomem0[2048]; /* 0x0800 */
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#endif
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};
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#endif
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#ifdef CONFIG_STRIDER_CPU
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struct ihs_fpga {
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u16 reflection_low; /* 0x0000 */
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u16 versions; /* 0x0002 */
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u16 fpga_version; /* 0x0004 */
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u16 fpga_features; /* 0x0006 */
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u16 reserved_0[1]; /* 0x0008 */
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u16 top_interrupt; /* 0x000a */
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u16 reserved_1[3]; /* 0x000c */
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u16 extended_control; /* 0x0012 */
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struct ihs_gpio gpio; /* 0x0014 */
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u16 mpc3w_control; /* 0x001a */
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u16 reserved_2[2]; /* 0x001c */
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struct ihs_io_ep ep; /* 0x0020 */
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u16 reserved_3[9]; /* 0x002e */
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u16 mc_int; /* 0x0040 */
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u16 mc_int_en; /* 0x0042 */
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u16 mc_status; /* 0x0044 */
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u16 mc_control; /* 0x0046 */
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u16 mc_tx_data; /* 0x0048 */
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u16 mc_tx_address; /* 0x004a */
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u16 mc_tx_cmd; /* 0x004c */
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u16 mc_res; /* 0x004e */
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u16 mc_rx_cmd_status; /* 0x0050 */
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u16 mc_rx_data; /* 0x0052 */
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u16 reserved_4[62]; /* 0x0054 */
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struct ihs_i2c i2c0; /* 0x00d0 */
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};
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#endif
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#ifdef CONFIG_STRIDER_CON
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struct ihs_fpga {
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u16 reflection_low; /* 0x0000 */
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u16 versions; /* 0x0002 */
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u16 fpga_version; /* 0x0004 */
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u16 fpga_features; /* 0x0006 */
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u16 reserved_0[1]; /* 0x0008 */
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u16 top_interrupt; /* 0x000a */
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u16 reserved_1[4]; /* 0x000c */
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struct ihs_gpio gpio; /* 0x0014 */
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u16 mpc3w_control; /* 0x001a */
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u16 reserved_2[2]; /* 0x001c */
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struct ihs_io_ep ep; /* 0x0020 */
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u16 reserved_3[9]; /* 0x002e */
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struct ihs_i2c i2c0; /* 0x0040 */
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u16 reserved_4[10]; /* 0x004c */
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u16 mc_int; /* 0x0060 */
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u16 mc_int_en; /* 0x0062 */
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u16 mc_status; /* 0x0064 */
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u16 mc_control; /* 0x0066 */
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u16 mc_tx_data; /* 0x0068 */
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u16 mc_tx_address; /* 0x006a */
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u16 mc_tx_cmd; /* 0x006c */
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u16 mc_res; /* 0x006e */
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u16 mc_rx_cmd_status; /* 0x0070 */
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u16 mc_rx_data; /* 0x0072 */
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u16 reserved_5[70]; /* 0x0074 */
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struct ihs_osd osd0; /* 0x0100 */
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u16 reserved_6[889]; /* 0x010e */
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u16 videomem0[2048]; /* 0x0800 */
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};
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#endif
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#ifdef CONFIG_DLVISION_10G
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struct ihs_fpga {
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u16 reflection_low; /* 0x0000 */
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u16 versions; /* 0x0002 */
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u16 fpga_version; /* 0x0004 */
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u16 fpga_features; /* 0x0006 */
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u16 reserved_0[10]; /* 0x0008 */
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u16 extended_interrupt; /* 0x001c */
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u16 reserved_1[29]; /* 0x001e */
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u16 mpc3w_control; /* 0x0058 */
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u16 reserved_2[3]; /* 0x005a */
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struct ihs_i2c i2c0; /* 0x0060 */
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u16 reserved_3[2]; /* 0x006c */
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struct ihs_i2c i2c1; /* 0x0070 */
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u16 reserved_4[194]; /* 0x007c */
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struct ihs_osd osd0; /* 0x0200 */
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u16 reserved_5[761]; /* 0x020e */
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u16 videomem0[2048]; /* 0x0800 */
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};
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#endif
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#endif
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