mirror of
https://github.com/brain-hackers/u-boot-brain
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83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
142 lines
4.7 KiB
C
142 lines
4.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright 2008-2014 Freescale Semiconductor, Inc.
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*/
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#ifndef FSL_DDR_MAIN_H
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#define FSL_DDR_MAIN_H
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#include <fsl_ddrc_version.h>
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#include <fsl_ddr_sdram.h>
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#include <fsl_ddr_dimm_params.h>
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#include <common_timing_params.h>
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#ifndef CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS
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/* All controllers are for main memory */
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#define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS CONFIG_SYS_NUM_DDR_CTLRS
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#endif
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#ifdef CONFIG_SYS_FSL_DDR_LE
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#define ddr_in32(a) in_le32(a)
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#define ddr_out32(a, v) out_le32(a, v)
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#define ddr_setbits32(a, v) setbits_le32(a, v)
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#define ddr_clrbits32(a, v) clrbits_le32(a, v)
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#define ddr_clrsetbits32(a, clear, set) clrsetbits_le32(a, clear, set)
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#else
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#define ddr_in32(a) in_be32(a)
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#define ddr_out32(a, v) out_be32(a, v)
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#define ddr_setbits32(a, v) setbits_be32(a, v)
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#define ddr_clrbits32(a, v) clrbits_be32(a, v)
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#define ddr_clrsetbits32(a, clear, set) clrsetbits_be32(a, clear, set)
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#endif
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u32 fsl_ddr_get_version(unsigned int ctrl_num);
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#if defined(CONFIG_DDR_SPD) || defined(CONFIG_SPD_EEPROM)
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/*
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* Bind the main DDR setup driver's generic names
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* to this specific DDR technology.
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*/
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static __inline__ int
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compute_dimm_parameters(const unsigned int ctrl_num,
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const generic_spd_eeprom_t *spd,
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dimm_params_t *pdimm,
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unsigned int dimm_number)
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{
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return ddr_compute_dimm_parameters(ctrl_num, spd, pdimm, dimm_number);
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}
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#endif
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/*
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* Data Structures
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*
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* All data structures have to be on the stack
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*/
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#define CONFIG_SYS_DIMM_SLOTS_PER_CTLR CONFIG_DIMM_SLOTS_PER_CTLR
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typedef struct {
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generic_spd_eeprom_t
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spd_installed_dimms[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_SYS_DIMM_SLOTS_PER_CTLR];
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struct dimm_params_s
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dimm_params[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_SYS_DIMM_SLOTS_PER_CTLR];
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memctl_options_t memctl_opts[CONFIG_SYS_NUM_DDR_CTLRS];
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common_timing_params_t common_timing_params[CONFIG_SYS_NUM_DDR_CTLRS];
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fsl_ddr_cfg_regs_t fsl_ddr_config_reg[CONFIG_SYS_NUM_DDR_CTLRS];
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unsigned int first_ctrl;
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unsigned int num_ctrls;
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unsigned long long mem_base;
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unsigned int dimm_slots_per_ctrl;
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int (*board_need_mem_reset)(void);
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void (*board_mem_reset)(void);
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void (*board_mem_de_reset)(void);
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} fsl_ddr_info_t;
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/* Compute steps */
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#define STEP_GET_SPD (1 << 0)
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#define STEP_COMPUTE_DIMM_PARMS (1 << 1)
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#define STEP_COMPUTE_COMMON_PARMS (1 << 2)
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#define STEP_GATHER_OPTS (1 << 3)
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#define STEP_ASSIGN_ADDRESSES (1 << 4)
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#define STEP_COMPUTE_REGS (1 << 5)
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#define STEP_PROGRAM_REGS (1 << 6)
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#define STEP_ALL 0xFFF
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unsigned long long
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fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step,
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unsigned int size_only);
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const char *step_to_string(unsigned int step);
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unsigned int compute_fsl_memctl_config_regs(const unsigned int ctrl_num,
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const memctl_options_t *popts,
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fsl_ddr_cfg_regs_t *ddr,
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const common_timing_params_t *common_dimm,
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const dimm_params_t *dimm_parameters,
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unsigned int dbw_capacity_adjust,
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unsigned int size_only);
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unsigned int compute_lowest_common_dimm_parameters(
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const unsigned int ctrl_num,
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const dimm_params_t *dimm_params,
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common_timing_params_t *outpdimm,
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unsigned int number_of_dimms);
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unsigned int populate_memctl_options(const common_timing_params_t *common_dimm,
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memctl_options_t *popts,
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dimm_params_t *pdimm,
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unsigned int ctrl_num);
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void check_interleaving_options(fsl_ddr_info_t *pinfo);
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unsigned int mclk_to_picos(const unsigned int ctrl_num, unsigned int mclk);
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unsigned int get_memory_clk_period_ps(const unsigned int ctrl_num);
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unsigned int picos_to_mclk(const unsigned int ctrl_num, unsigned int picos);
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void fsl_ddr_set_lawbar(
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const common_timing_params_t *memctl_common_params,
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unsigned int memctl_interleaved,
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unsigned int ctrl_num);
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void fsl_ddr_sync_memctl_refresh(unsigned int first_ctrl,
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unsigned int last_ctrl);
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int fsl_ddr_interactive_env_var_exists(void);
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unsigned long long fsl_ddr_interactive(fsl_ddr_info_t *pinfo, int var_is_set);
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void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd,
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unsigned int ctrl_num, unsigned int dimm_slots_per_ctrl);
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int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
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unsigned int check_fsl_memctl_config_regs(const fsl_ddr_cfg_regs_t *ddr);
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void board_add_ram_info(int use_default);
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/* processor specific function */
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void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
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unsigned int ctrl_num, int step);
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void remove_unused_controllers(fsl_ddr_info_t *info);
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/* board specific function */
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int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
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unsigned int controller_number,
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unsigned int dimm_number);
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void update_spd_address(unsigned int ctrl_num,
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unsigned int slot,
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unsigned int *addr);
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void erratum_a009942_check_cpo(void);
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#endif
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