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https://github.com/brain-hackers/u-boot-brain
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07ce19f5e9
Add PCIe Gen4 driver for the NXP Layerscape SoCs. This PCIe controller is based on the Mobiveil IP, which is compatible with the PCI Express™ Base Specification, Revision 4.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Bao Xiaowei <Xiaowei.Bao@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
265 lines
7.4 KiB
C
265 lines
7.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright 2018-2019 NXP
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*
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* PCIe Gen4 driver for NXP Layerscape SoCs
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* Author: Hou Zhiqiang <Minder.Hou@gmail.com>
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*/
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#ifndef _PCIE_LAYERSCAPE_GEN4_H_
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#define _PCIE_LAYERSCAPE_GEN4_H_
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#include <pci.h>
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#include <dm.h>
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#ifndef CONFIG_SYS_PCI_MEMORY_SIZE
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#define CONFIG_SYS_PCI_MEMORY_SIZE (4 * 1024 * 1024 * 1024ULL)
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#endif
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#ifndef CONFIG_SYS_PCI_EP_MEMORY_BASE
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#define CONFIG_SYS_PCI_EP_MEMORY_BASE CONFIG_SYS_LOAD_ADDR
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#endif
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#define PCIE_PF_NUM 2
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#define PCIE_VF_NUM 32
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#define LS_G4_PF0 0
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#define LS_G4_PF1 1
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#define PF_BAR_NUM 4
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#define VF_BAR_NUM 4
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#define PCIE_BAR_SIZE (8 * 1024) /* 8K */
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#define PCIE_BAR0_SIZE PCIE_BAR_SIZE
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#define PCIE_BAR1_SIZE PCIE_BAR_SIZE
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#define PCIE_BAR2_SIZE PCIE_BAR_SIZE
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#define PCIE_BAR4_SIZE PCIE_BAR_SIZE
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#define SIZE_1T (1024 * 1024 * 1024 * 1024ULL)
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/* GPEX CSR */
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#define GPEX_CLASSCODE 0x474
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#define GPEX_CLASSCODE_SHIFT 16
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#define GPEX_CLASSCODE_MASK 0xffff
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#define GPEX_CFG_READY 0x4b0
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#define PCIE_CONFIG_READY BIT(0)
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#define GPEX_BAR_ENABLE 0x4d4
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#define GPEX_BAR_SIZE_LDW 0x4d8
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#define GPEX_BAR_SIZE_UDW 0x4dC
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#define GPEX_BAR_SELECT 0x4e0
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#define BAR_POS(bar, pf, vf_bar) \
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((bar) + (pf) * PF_BAR_NUM + (vf_bar) * PCIE_PF_NUM * PF_BAR_NUM)
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#define GPEX_SRIOV_INIT_VFS_TOTAL_VF(pf) (0x644 + (pf) * 4)
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#define TTL_VF_MASK 0xffff
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#define TTL_VF_SHIFT 16
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#define INI_VF_MASK 0xffff
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#define INI_VF_SHIFT 0
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#define GPEX_SRIOV_VF_OFFSET_STRIDE(pf) (0x704 + (pf) * 4)
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/* PAB CSR */
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#define PAB_CTRL 0x808
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#define PAB_CTRL_APIO_EN BIT(0)
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#define PAB_CTRL_PPIO_EN BIT(1)
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#define PAB_CTRL_MAX_BRST_LEN_SHIFT 4
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#define PAB_CTRL_MAX_BRST_LEN_MASK 0x3
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#define PAB_CTRL_PAGE_SEL_SHIFT 13
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#define PAB_CTRL_PAGE_SEL_MASK 0x3f
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#define PAB_CTRL_FUNC_SEL_SHIFT 19
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#define PAB_CTRL_FUNC_SEL_MASK 0x1ff
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#define PAB_RST_CTRL 0x820
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#define PAB_BR_STAT 0x80c
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/* AXI PIO Engines */
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#define PAB_AXI_PIO_CTRL(idx) (0x840 + 0x10 * (idx))
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#define APIO_EN BIT(0)
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#define MEM_WIN_EN BIT(1)
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#define IO_WIN_EN BIT(2)
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#define CFG_WIN_EN BIT(3)
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#define PAB_AXI_PIO_STAT(idx) (0x844 + 0x10 * (idx))
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#define PAB_AXI_PIO_SL_CMD_STAT(idx) (0x848 + 0x10 * (idx))
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#define PAB_AXI_PIO_SL_ADDR_STAT(idx) (0x84c + 0x10 * (idx))
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#define PAB_AXI_PIO_SL_EXT_ADDR_STAT(idx) (0xb8a0 + 0x4 * (idx))
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/* PEX PIO Engines */
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#define PAB_PEX_PIO_CTRL(idx) (0x8c0 + 0x10 * (idx))
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#define PPIO_EN BIT(0)
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#define PAB_PEX_PIO_STAT(idx) (0x8c4 + 0x10 * (idx))
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#define PAB_PEX_PIO_MT_STAT(idx) (0x8c8 + 0x10 * (idx))
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#define INDIRECT_ADDR_BNDRY 0xc00
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#define PAGE_IDX_SHIFT 10
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#define PAGE_ADDR_MASK 0x3ff
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#define OFFSET_TO_PAGE_IDX(off) \
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(((off) >> PAGE_IDX_SHIFT) & PAB_CTRL_PAGE_SEL_MASK)
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#define OFFSET_TO_PAGE_ADDR(off) \
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(((off) & PAGE_ADDR_MASK) | INDIRECT_ADDR_BNDRY)
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/* APIO WINs */
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#define PAB_AXI_AMAP_CTRL(idx) (0xba0 + 0x10 * (idx))
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#define PAB_EXT_AXI_AMAP_SIZE(idx) (0xbaf0 + 0x4 * (idx))
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#define PAB_AXI_AMAP_AXI_WIN(idx) (0xba4 + 0x10 * (idx))
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#define PAB_EXT_AXI_AMAP_AXI_WIN(idx) (0x80a0 + 0x4 * (idx))
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#define PAB_AXI_AMAP_PEX_WIN_L(idx) (0xba8 + 0x10 * (idx))
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#define PAB_AXI_AMAP_PEX_WIN_H(idx) (0xbac + 0x10 * (idx))
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#define PAB_AXI_AMAP_PCI_HDR_PARAM(idx) (0x5ba0 + 0x4 * (idx))
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#define FUNC_NUM_PCIE_MASK GENMASK(7, 0)
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#define AXI_AMAP_CTRL_EN BIT(0)
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#define AXI_AMAP_CTRL_TYPE_SHIFT 1
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#define AXI_AMAP_CTRL_TYPE_MASK 0x3
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#define AXI_AMAP_CTRL_SIZE_SHIFT 10
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#define AXI_AMAP_CTRL_SIZE_MASK 0x3fffff
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#define PAB_TARGET_BUS(x) (((x) & 0xff) << 24)
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#define PAB_TARGET_DEV(x) (((x) & 0x1f) << 19)
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#define PAB_TARGET_FUNC(x) (((x) & 0x7) << 16)
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#define PAB_AXI_TYPE_CFG 0x00
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#define PAB_AXI_TYPE_IO 0x01
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#define PAB_AXI_TYPE_MEM 0x02
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#define PAB_AXI_TYPE_ATOM 0x03
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#define PAB_WINS_NUM 256
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/* PPIO WINs RC mode */
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#define PAB_PEX_AMAP_CTRL(idx) (0x4ba0 + 0x10 * (idx))
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#define PAB_EXT_PEX_AMAP_SIZE(idx) (0xbef0 + 0x04 * (idx))
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#define PAB_PEX_AMAP_AXI_WIN(idx) (0x4ba4 + 0x10 * (idx))
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#define PAB_EXT_PEX_AMAP_AXI_WIN(idx) (0xb4a0 + 0x04 * (idx))
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#define PAB_PEX_AMAP_PEX_WIN_L(idx) (0x4ba8 + 0x10 * (idx))
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#define PAB_PEX_AMAP_PEX_WIN_H(idx) (0x4bac + 0x10 * (idx))
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#define IB_TYPE_MEM_F 0x2
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#define IB_TYPE_MEM_NF 0x3
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#define PEX_AMAP_CTRL_TYPE_SHIFT 0x1
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#define PEX_AMAP_CTRL_EN_SHIFT 0x0
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#define PEX_AMAP_CTRL_TYPE_MASK 0x3
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#define PEX_AMAP_CTRL_EN_MASK 0x1
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/* PPIO WINs EP mode */
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#define PAB_PEX_BAR_AMAP(pf, bar) \
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(0x1ba0 + 0x20 * (pf) + 4 * (bar))
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#define BAR_AMAP_EN BIT(0)
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#define PAB_EXT_PEX_BAR_AMAP(pf, bar) \
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(0x84a0 + 0x20 * (pf) + 4 * (bar))
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/* CCSR registers */
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#define PCIE_LINK_CTRL_STA 0x5c
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#define PCIE_LINK_SPEED_SHIFT 16
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#define PCIE_LINK_SPEED_MASK 0x0f
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#define PCIE_LINK_WIDTH_SHIFT 20
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#define PCIE_LINK_WIDTH_MASK 0x3f
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#define PCIE_SRIOV_CAPABILITY 0x2a0
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#define PCIE_SRIOV_VF_OFFSET_STRIDE 0x2b4
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/* LUT registers */
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#define PCIE_LUT_UDR(n) (0x800 + (n) * 8)
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#define PCIE_LUT_LDR(n) (0x804 + (n) * 8)
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#define PCIE_LUT_ENABLE BIT(31)
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#define PCIE_LUT_ENTRY_COUNT 32
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/* PF control registers */
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#define PCIE_LTSSM_STA 0x7fc
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#define LTSSM_STATE_MASK 0x7f
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#define LTSSM_PCIE_L0 0x2d /* L0 state */
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#define PCIE_SRDS_PRTCL(idx) (PCIE1 + (idx))
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#define PCIE_SYS_BASE_ADDR 0x3400000
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#define PCIE_CCSR_SIZE 0x0100000
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struct ls_pcie_g4 {
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int idx;
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struct list_head list;
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struct udevice *bus;
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struct fdt_resource ccsr_res;
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struct fdt_resource cfg_res;
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struct fdt_resource lut_res;
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struct fdt_resource pf_ctrl_res;
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void __iomem *ccsr;
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void __iomem *cfg;
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void __iomem *lut;
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void __iomem *pf_ctrl;
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bool big_endian;
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bool enabled;
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int next_lut_index;
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struct pci_controller hose;
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int stream_id_cur;
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int mode;
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int sriov_support;
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};
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extern struct list_head ls_pcie_g4_list;
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static inline void lut_writel(struct ls_pcie_g4 *pcie, unsigned int value,
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unsigned int offset)
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{
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if (pcie->big_endian)
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out_be32(pcie->lut + offset, value);
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else
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out_le32(pcie->lut + offset, value);
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}
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static inline u32 lut_readl(struct ls_pcie_g4 *pcie, unsigned int offset)
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{
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if (pcie->big_endian)
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return in_be32(pcie->lut + offset);
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else
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return in_le32(pcie->lut + offset);
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}
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static inline void ccsr_set_page(struct ls_pcie_g4 *pcie, u8 pg_idx)
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{
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u32 val;
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val = in_le32(pcie->ccsr + PAB_CTRL);
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val &= ~(PAB_CTRL_PAGE_SEL_MASK << PAB_CTRL_PAGE_SEL_SHIFT);
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val |= (pg_idx & PAB_CTRL_PAGE_SEL_MASK) << PAB_CTRL_PAGE_SEL_SHIFT;
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out_le32(pcie->ccsr + PAB_CTRL, val);
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}
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static inline unsigned int ccsr_readl(struct ls_pcie_g4 *pcie, u32 offset)
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{
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if (offset < INDIRECT_ADDR_BNDRY) {
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ccsr_set_page(pcie, 0);
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return in_le32(pcie->ccsr + offset);
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}
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ccsr_set_page(pcie, OFFSET_TO_PAGE_IDX(offset));
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return in_le32(pcie->ccsr + OFFSET_TO_PAGE_ADDR(offset));
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}
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static inline void ccsr_writel(struct ls_pcie_g4 *pcie, u32 offset, u32 value)
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{
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if (offset < INDIRECT_ADDR_BNDRY) {
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ccsr_set_page(pcie, 0);
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out_le32(pcie->ccsr + offset, value);
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} else {
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ccsr_set_page(pcie, OFFSET_TO_PAGE_IDX(offset));
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out_le32(pcie->ccsr + OFFSET_TO_PAGE_ADDR(offset), value);
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}
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}
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static inline unsigned int pf_ctrl_readl(struct ls_pcie_g4 *pcie, u32 offset)
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{
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if (pcie->big_endian)
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return in_be32(pcie->pf_ctrl + offset);
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else
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return in_le32(pcie->pf_ctrl + offset);
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}
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static inline void pf_ctrl_writel(struct ls_pcie_g4 *pcie, u32 offset,
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u32 value)
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{
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if (pcie->big_endian)
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out_be32(pcie->pf_ctrl + offset, value);
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else
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out_le32(pcie->pf_ctrl + offset, value);
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}
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#endif /* _PCIE_LAYERSCAPE_GEN4_H_ */
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