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https://github.com/brain-hackers/u-boot-brain
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0ea6cc1253
To make SPL_OF_CONTROL work on ARM64 SoCs, _image_binary_end must be defined in the linker script. LD spl/u-boot-spl lib/built-in.o: In function `fdtdec_setup': lib/fdtdec.c:1186: undefined reference to `_image_binary_end' lib/fdtdec.c:1186: undefined reference to `_image_binary_end' make[1]: *** [spl/u-boot-spl] Error 1 make: *** [spl/u-boot-spl] Error 2 Note: CONFIG_SPL_SEPARATE_BSS must be defined as well on ARM64 SoCs. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Tom Rini <trini@konsulko.com>
80 lines
1.4 KiB
Plaintext
80 lines
1.4 KiB
Plaintext
/*
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* (C) Copyright 2013
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* David Feng <fenghua@phytium.com.cn>
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*
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* (C) Copyright 2002
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* Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
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*
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* (C) Copyright 2010
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* Texas Instruments, <www.ti.com>
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* Aneesh V <aneesh@ti.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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MEMORY { .sram : ORIGIN = CONFIG_SPL_TEXT_BASE,
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LENGTH = CONFIG_SPL_MAX_SIZE }
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MEMORY { .sdram : ORIGIN = CONFIG_SPL_BSS_START_ADDR,
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LENGTH = CONFIG_SPL_BSS_MAX_SIZE }
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OUTPUT_FORMAT("elf64-littleaarch64", "elf64-littleaarch64", "elf64-littleaarch64")
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OUTPUT_ARCH(aarch64)
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ENTRY(_start)
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SECTIONS
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{
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.text : {
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. = ALIGN(8);
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*(.__image_copy_start)
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CPUDIR/start.o (.text*)
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*(.text*)
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} >.sram
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.rodata : {
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. = ALIGN(8);
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*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
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} >.sram
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.data : {
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. = ALIGN(8);
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*(.data*)
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} >.sram
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.u_boot_list : {
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. = ALIGN(8);
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KEEP(*(SORT(.u_boot_list*)));
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} >.sram
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.image_copy_end : {
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. = ALIGN(8);
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*(.__image_copy_end)
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} >.sram
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.end : {
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. = ALIGN(8);
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*(.__end)
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} >.sram
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_image_binary_end = .;
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.bss_start : {
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. = ALIGN(8);
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KEEP(*(.__bss_start));
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} >.sdram
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.bss : {
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*(.bss*)
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. = ALIGN(8);
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} >.sdram
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.bss_end : {
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KEEP(*(.__bss_end));
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} >.sdram
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/DISCARD/ : { *(.dynsym) }
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/DISCARD/ : { *(.dynstr*) }
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/DISCARD/ : { *(.dynamic*) }
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/DISCARD/ : { *(.plt*) }
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/DISCARD/ : { *(.interp*) }
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/DISCARD/ : { *(.gnu*) }
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}
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