mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-14 23:26:16 +09:00
3c195299a8
The default rproc list currently used by A72 U-Boot to boot various remote processors include the Main R5FSS0 (Split-mode) Core1, Main R5FSS1 (LockStep mode) Core0 and the three DSPs. The Main R5FSS1 cluster is configured for Split mode by default in the dts now, so add the Main R5FSS1 Core1 (rproc #5) to the default rproc boot list. This core is now booted after the Main R5FSS1 Core0 and before the DSPs. The order of the rprocs to boot can always be changed at runtime if desired by overwriting the 'rproc_fw_binaries' environment variable at U-boot prompt. Note that the R5FSS Core1 cannot be booted before its associated Core0. Signed-off-by: Suman Anna <s-anna@ti.com>
158 lines
5.2 KiB
C
158 lines
5.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Configuration header file for K3 J721E EVM
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*
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* Copyright (C) 2018-2019 Texas Instruments Incorporated - http://www.ti.com/
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* Lokesh Vutla <lokeshvutla@ti.com>
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*/
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#ifndef __CONFIG_J721E_EVM_H
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#define __CONFIG_J721E_EVM_H
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#include <linux/sizes.h>
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#include <config_distro_bootcmd.h>
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#include <environment/ti/mmc.h>
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#include <environment/ti/k3_rproc.h>
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#include <environment/ti/ufs.h>
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#include <environment/ti/k3_dfu.h>
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/* DDR Configuration */
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#define CONFIG_SYS_SDRAM_BASE1 0x880000000
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/* SPL Loader Configuration */
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#if defined(CONFIG_TARGET_J721E_A72_EVM) || defined(CONFIG_TARGET_J7200_A72_EVM)
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#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SPL_TEXT_BASE + \
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CONFIG_SYS_K3_NON_SECURE_MSRAM_SIZE)
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#define CONFIG_SYS_UBOOT_BASE 0x50280000
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/* Image load address in RAM for DFU boot*/
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#else
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#define CONFIG_SYS_UBOOT_BASE 0x50080000
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/*
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* Maximum size in memory allocated to the SPL BSS. Keep it as tight as
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* possible (to allow the build to go through), as this directly affects
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* our memory footprint. The less we use for BSS the more we have available
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* for everything else.
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*/
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#define CONFIG_SPL_BSS_MAX_SIZE 0xA000
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/*
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* Link BSS to be within SPL in a dedicated region located near the top of
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* the MCU SRAM, this way making it available also before relocation. Note
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* that we are not using the actual top of the MCU SRAM as there is a memory
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* location filled in by the boot ROM that we want to read out without any
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* interference from the C context.
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*/
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#define CONFIG_SPL_BSS_START_ADDR (CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX -\
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CONFIG_SPL_BSS_MAX_SIZE)
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/* Set the stack right below the SPL BSS section */
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#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SPL_BSS_START_ADDR
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/* Configure R5 SPL post-relocation malloc pool in DDR */
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#define CONFIG_SYS_SPL_MALLOC_START 0x84000000
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#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_16M
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/* Image load address in RAM for DFU boot*/
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#endif
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#ifdef CONFIG_SYS_K3_SPL_ATF
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#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "tispl.bin"
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#endif
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#define CONFIG_SPL_MAX_SIZE CONFIG_SYS_K3_MAX_DOWNLODABLE_IMAGE_SIZE
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#define CONFIG_SYS_BOOTM_LEN SZ_64M
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#define CONFIG_CQSPI_REF_CLK 133333333
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/* HyperFlash related configuration */
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#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 1
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/* U-Boot general configuration */
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#define EXTRA_ENV_J721E_BOARD_SETTINGS \
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"default_device_tree=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \
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"findfdt=" \
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"setenv name_fdt ${default_device_tree};" \
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"setenv fdtfile ${name_fdt}\0" \
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"loadaddr=0x80080000\0" \
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"fdtaddr=0x82000000\0" \
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"overlayaddr=0x83000000\0" \
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"name_kern=Image\0" \
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"console=ttyS2,115200n8\0" \
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"args_all=setenv optargs earlycon=ns16550a,mmio32,0x02800000 " \
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"${mtdparts}\0" \
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"run_kern=booti ${loadaddr} ${rd_spec} ${fdtaddr}\0"
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#define PARTS_DEFAULT \
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/* Linux partitions */ \
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"uuid_disk=${uuid_gpt_disk};" \
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"name=rootfs,start=0,size=-,uuid=${uuid_gpt_rootfs}\0"
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/* U-Boot MMC-specific configuration */
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#define EXTRA_ENV_J721E_BOARD_SETTINGS_MMC \
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"boot=mmc\0" \
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"mmcdev=1\0" \
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"bootpart=1:2\0" \
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"bootdir=/boot\0" \
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"addr_mainr5f0_0load=88000000\0" \
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"name_mainr5f0_0fw=/lib/firmware/j7-main-r5f0_0-fw\0" \
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"addr_mcur5f0_0load=89000000\0" \
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"name_mcur5f0_0fw=/lib/firmware/j7-mcu-r5f0_0-fw\0" \
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"rd_spec=-\0" \
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"init_mmc=run args_all args_mmc\0" \
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"get_fdt_mmc=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${name_fdt}\0" \
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"get_overlay_mmc=" \
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"fdt address ${fdtaddr};" \
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"fdt resize 0x100000;" \
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"for overlay in $name_overlays;" \
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"do;" \
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"load mmc ${bootpart} ${overlayaddr} ${bootdir}/${overlay} && " \
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"fdt apply ${overlayaddr};" \
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"done;\0" \
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"partitions=" PARTS_DEFAULT \
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"get_kern_mmc=load mmc ${bootpart} ${loadaddr} " \
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"${bootdir}/${name_kern}\0" \
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"get_fit_mmc=load mmc ${bootpart} ${addr_fit} " \
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"${bootdir}/${name_fit}\0" \
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"partitions=" PARTS_DEFAULT
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#ifdef DEFAULT_RPROCS
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#undef DEFAULT_RPROCS
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#endif
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#define DEFAULT_RPROCS "" \
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"3 /lib/firmware/j7-main-r5f0_1-fw " \
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"4 /lib/firmware/j7-main-r5f1_0-fw " \
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"5 /lib/firmware/j7-main-r5f1_1-fw " \
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"6 /lib/firmware/j7-c66_0-fw " \
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"7 /lib/firmware/j7-c66_1-fw " \
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"8 /lib/firmware/j7-c71_0-fw "
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/* set default dfu_bufsiz to 128KB (sector size of OSPI) */
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#define EXTRA_ENV_DFUARGS \
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"dfu_bufsiz=0x20000\0" \
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DFU_ALT_INFO_MMC \
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DFU_ALT_INFO_EMMC \
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DFU_ALT_INFO_RAM \
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DFU_ALT_INFO_OSPI
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#if defined(CONFIG_TARGET_J721E_A72_EVM) || defined(CONFIG_TARGET_J7200_A72_EVM)
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#define EXTRA_ENV_J721E_BOARD_SETTINGS_MTD \
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"mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \
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"mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0"
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#else
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#define EXTRA_ENV_J721E_BOARD_SETTINGS_MTD
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#endif
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/* Incorporate settings into the U-Boot environment */
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#define CONFIG_EXTRA_ENV_SETTINGS \
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DEFAULT_MMC_TI_ARGS \
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DEFAULT_FIT_TI_ARGS \
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EXTRA_ENV_J721E_BOARD_SETTINGS \
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EXTRA_ENV_J721E_BOARD_SETTINGS_MMC \
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EXTRA_ENV_RPROC_SETTINGS \
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EXTRA_ENV_DFUARGS \
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DEFAULT_UFS_TI_ARGS \
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EXTRA_ENV_J721E_BOARD_SETTINGS_MTD
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/* Now for the remaining common defines */
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#include <configs/ti_armv7_common.h>
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/* MMC ENV related defines */
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#endif /* __CONFIG_J721E_EVM_H */
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