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![]() microblaze: - Align defconfig zynq: - Rework fpga initialization and cpuinfo handling zynqmp: - Add ZynqMP R5 support - Wire and enable watchdog on zcu100-revC - Setup MMU map for DDR at run time - Show board info based on DT and cleanup IDENT_STRING zynqmp tools: - Add read partition support - Add initial support for Xilinx bif format for boot.bin generation mmc: - Fix get_timer usage on 64bit cpus - Add support for SD3.0 UHS mode nand-zynq: - Add support for 16bit buswidth - Use address cycles from onfi params scsi: - convert ceva sata to UCLASS_AHCI timer: - Add Cadence TTC for ZynqMP r5 watchdog: - Minor cadence driver cleanup -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iEYEABECAAYFAlr1ldMACgkQykllyylKDCHioACghoJw6+NqsZXl8zGWRP38yZ5K mvgAnihfOQq125mpKPZmcc5yt6wVwYIU =8ji9 -----END PGP SIGNATURE----- Merge tag 'xilinx-for-v2018.07' of git://www.denx.de/git/u-boot-microblaze Xilinx changes for v2018.07 microblaze: - Align defconfig zynq: - Rework fpga initialization and cpuinfo handling zynqmp: - Add ZynqMP R5 support - Wire and enable watchdog on zcu100-revC - Setup MMU map for DDR at run time - Show board info based on DT and cleanup IDENT_STRING zynqmp tools: - Add read partition support - Add initial support for Xilinx bif format for boot.bin generation mmc: - Fix get_timer usage on 64bit cpus - Add support for SD3.0 UHS mode nand-zynq: - Add support for 16bit buswidth - Use address cycles from onfi params scsi: - convert ceva sata to UCLASS_AHCI timer: - Add Cadence TTC for ZynqMP r5 watchdog: - Minor cadence driver cleanup |
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.. | ||
fsl-layerscape | ||
hisilicon | ||
s32v234 | ||
zynqmp | ||
cache_v8.c | ||
cache.S | ||
config.mk | ||
cpu-dt.c | ||
cpu.c | ||
exceptions.S | ||
fwcall.c | ||
generic_timer.c | ||
Kconfig | ||
linux-kernel-image-header-vars.h | ||
lowlevel_init.S | ||
Makefile | ||
psci.S | ||
sec_firmware_asm.S | ||
sec_firmware.c | ||
smccc-call.S | ||
spin_table_v8.S | ||
spin_table.c | ||
start.S | ||
tlb.S | ||
transition.S | ||
u-boot-spl.lds | ||
u-boot.lds |