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![York Sun](/assets/img/avatar_default.png)
Update the timing table to support more rank density, based on the theory that similar density DIMMs have similar clock adjust and write level start timing. Update the timing for 1600 and 1866 MT/s. Tested with Micron MT18JSF1G72AZ-1G9E1 DIMMs, iDIMM M3CN-4GMJ3C0C-M92. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
199 lines
5.9 KiB
C
199 lines
5.9 KiB
C
/*
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* Copyright 2012 Freescale Semiconductor, Inc.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* Version 2 or later as published by the Free Software Foundation.
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*/
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#include <common.h>
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#include <i2c.h>
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#include <hwconfig.h>
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#include <asm/mmu.h>
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#include <asm/fsl_ddr_sdram.h>
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#include <asm/fsl_ddr_dimm_params.h>
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#include <asm/fsl_law.h>
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DECLARE_GLOBAL_DATA_PTR;
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struct board_specific_parameters {
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u32 n_ranks;
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u32 datarate_mhz_high;
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u32 rank_gb;
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u32 clk_adjust;
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u32 wrlvl_start;
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u32 wrlvl_ctl_2;
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u32 wrlvl_ctl_3;
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u32 cpo;
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u32 write_data_delay;
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u32 force_2T;
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};
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/*
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* This table contains all valid speeds we want to override with board
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* specific parameters. datarate_mhz_high values need to be in ascending order
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* for each n_ranks group.
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*/
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static const struct board_specific_parameters udimm0[] = {
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/*
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* memory controller 0
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* num| hi| rank| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T
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* ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay |
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*/
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{2, 1350, 4, 4, 8, 0x0809090b, 0x0c0c0d0a, 0xff, 2, 0},
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{2, 1350, 0, 5, 7, 0x0709090b, 0x0c0c0d09, 0xff, 2, 0},
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{2, 1666, 4, 4, 8, 0x080a0a0d, 0x0d10100b, 0xff, 2, 0},
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{2, 1666, 0, 5, 7, 0x080a0a0c, 0x0d0d0e0a, 0xff, 2, 0},
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{2, 1900, 0, 4, 8, 0x090a0b0e, 0x0f11120c, 0xff, 2, 0},
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{2, 2140, 0, 4, 8, 0x090a0b0e, 0x0f11120c, 0xff, 2, 0},
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{1, 1350, 0, 5, 8, 0x0809090b, 0x0c0c0d0a, 0xff, 2, 0},
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{1, 1700, 0, 5, 8, 0x080a0a0c, 0x0c0d0e0a, 0xff, 2, 0},
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{1, 1900, 0, 4, 8, 0x080a0a0c, 0x0e0e0f0a, 0xff, 2, 0},
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{1, 2140, 0, 4, 8, 0x090a0b0c, 0x0e0f100b, 0xff, 2, 0},
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{}
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};
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/*
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* The three slots have slightly different timing. The center values are good
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* for all slots. We use identical speed tables for them. In future use, if
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* DIMMs require separated tables, make more entries as needed.
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*/
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static const struct board_specific_parameters *udimms[] = {
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udimm0,
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};
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static const struct board_specific_parameters rdimm0[] = {
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/*
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* memory controller 0
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* num| hi| rank| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T
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* ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay |
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*/
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{4, 1350, 0, 5, 9, 0x08070605, 0x07080805, 0xff, 2, 0},
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{4, 1666, 0, 5, 8, 0x08070605, 0x07080805, 0xff, 2, 0},
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{4, 2140, 0, 5, 8, 0x08070605, 0x07081805, 0xff, 2, 0},
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{2, 1350, 0, 5, 7, 0x0809090b, 0x0c0c0d09, 0xff, 2, 0},
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{2, 1666, 0, 5, 8, 0x080a0a0c, 0x0c0d0e0a, 0xff, 2, 0},
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{2, 2140, 0, 5, 8, 0x090a0b0c, 0x0e0f100b, 0xff, 2, 0},
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{1, 1350, 0, 5, 8, 0x0809090b, 0x0c0c0d0a, 0xff, 2, 0},
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{1, 1700, 0, 5, 8, 0x080a0a0c, 0x0c0d0e0a, 0xff, 2, 0},
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{1, 1900, 0, 4, 8, 0x080a0a0c, 0x0e0e0f0a, 0xff, 2, 0},
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{1, 2140, 0, 4, 8, 0x090a0b0c, 0x0e0f100b, 0xff, 2, 0},
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{}
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};
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/*
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* The three slots have slightly different timing. See comments above.
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*/
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static const struct board_specific_parameters *rdimms[] = {
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rdimm0,
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};
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void fsl_ddr_board_options(memctl_options_t *popts,
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dimm_params_t *pdimm,
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unsigned int ctrl_num)
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{
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const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
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ulong ddr_freq;
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if (ctrl_num > 2) {
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printf("Not supported controller number %d\n", ctrl_num);
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return;
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}
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if (!pdimm->n_ranks)
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return;
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/*
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* we use identical timing for all slots. If needed, change the code
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* to pbsp = rdimms[ctrl_num] or pbsp = udimms[ctrl_num];
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*/
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if (popts->registered_dimm_en)
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pbsp = rdimms[0];
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else
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pbsp = udimms[0];
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/* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
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* freqency and n_banks specified in board_specific_parameters table.
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*/
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ddr_freq = get_ddr_freq(0) / 1000000;
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while (pbsp->datarate_mhz_high) {
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if (pbsp->n_ranks == pdimm->n_ranks &&
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(pdimm->rank_density >> 30) >= pbsp->rank_gb) {
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if (ddr_freq <= pbsp->datarate_mhz_high) {
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popts->cpo_override = pbsp->cpo;
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popts->write_data_delay =
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pbsp->write_data_delay;
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popts->clk_adjust = pbsp->clk_adjust;
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popts->wrlvl_start = pbsp->wrlvl_start;
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popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
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popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
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popts->twoT_en = pbsp->force_2T;
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goto found;
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}
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pbsp_highest = pbsp;
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}
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pbsp++;
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}
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if (pbsp_highest) {
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printf("Error: board specific timing not found "
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"for data rate %lu MT/s\n"
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"Trying to use the highest speed (%u) parameters\n",
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ddr_freq, pbsp_highest->datarate_mhz_high);
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popts->cpo_override = pbsp_highest->cpo;
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popts->write_data_delay = pbsp_highest->write_data_delay;
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popts->clk_adjust = pbsp_highest->clk_adjust;
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popts->wrlvl_start = pbsp_highest->wrlvl_start;
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popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
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popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
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popts->twoT_en = pbsp_highest->force_2T;
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} else {
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panic("DIMM is not supported by this board");
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}
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found:
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debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n"
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"\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, "
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"wrlvl_ctrl_3 0x%x\n",
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pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb,
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pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2,
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pbsp->wrlvl_ctl_3);
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/*
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* Factors to consider for half-strength driver enable:
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* - number of DIMMs installed
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*/
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popts->half_strength_driver_enable = 0;
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/*
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* Write leveling override
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*/
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popts->wrlvl_override = 1;
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popts->wrlvl_sample = 0xf;
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/*
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* Rtt and Rtt_WR override
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*/
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popts->rtt_override = 0;
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/* Enable ZQ calibration */
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popts->zq_en = 1;
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/* DHC_EN =1, ODT = 75 Ohm */
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popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
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popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
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}
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phys_size_t initdram(int board_type)
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{
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phys_size_t dram_size;
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puts("Initializing....using SPD\n");
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dram_size = fsl_ddr_sdram();
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dram_size = setup_ddr_tlbs(dram_size / 0x100000);
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dram_size *= 0x100000;
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puts(" DDR: ");
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return dram_size;
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}
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