mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-08 12:16:16 +09:00
f38f5f4bcf
This patch adds board support for the Toradex Apalis TK1 a computer on module which can be used on different carrier boards. The module consists of a Tegra TK1 SoC, a PMIC solution, 2 GB of DDR3L RAM, a bunch of level shifters, an eMMC, a TMP451 temperature sensor chip, an I210 gigabit Ethernet controller and a SGTL5000 audio codec. Furthermore, there is a Kinetis MK20DN512 companion micro controller for analogue, CAN and resistive touch functionality. For the sake of ease of use we do not distinguish between different carrier boards for now as the base module features are deemed sufficient enough for regular booting. The following functionality is working so far: - eMMC boot, environment storage and Toradex factory config block - Gigabit Ethernet - MMC/SD cards (both MMC1 as well as SD1 slot) - USB client/host (dual role OTG port as client e.g. for DFU/UMS or host, other two ports as host) Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
118 lines
3.8 KiB
C
118 lines
3.8 KiB
C
/*
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* Copyright (c) 2012-2016 Toradex, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch-tegra/tegra_i2c.h>
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#include "as3722_init.h"
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/* AS3722-PMIC-specific early init code - get CPU rails up, etc */
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void tegra_i2c_ll_write_addr(uint addr, uint config)
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{
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struct i2c_ctlr *reg = (struct i2c_ctlr *)TEGRA_DVC_BASE;
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writel(addr, ®->cmd_addr0);
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writel(config, ®->cnfg);
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}
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void tegra_i2c_ll_write_data(uint data, uint config)
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{
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struct i2c_ctlr *reg = (struct i2c_ctlr *)TEGRA_DVC_BASE;
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writel(data, ®->cmd_data1);
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writel(config, ®->cnfg);
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}
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void pmic_enable_cpu_vdd(void)
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{
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debug("%s entry\n", __func__);
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#ifdef AS3722_SD1VOLTAGE_DATA
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/* Set up VDD_CORE, for boards where OTP is incorrect*/
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debug("%s: Setting VDD_CORE via AS3722 reg 1\n", __func__);
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/* Configure VDD_CORE via the AS3722 PMIC on the PWR I2C bus */
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tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
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tegra_i2c_ll_write_data(AS3722_SD1VOLTAGE_DATA, I2C_SEND_2_BYTES);
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/*
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* Don't write SDCONTROL - it's already 0x7F, i.e. all SDs enabled.
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* tegra_i2c_ll_write_data(AS3722_SD1CONTROL_DATA, I2C_SEND_2_BYTES);
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*/
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udelay(10 * 1000);
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#endif
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debug("%s: Setting VDD_CPU to 1.0V via AS3722 reg 0/4D\n", __func__);
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/*
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* Bring up VDD_CPU via the AS3722 PMIC on the PWR I2C bus.
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* First set VDD to 1.0V, then enable the VDD regulator.
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*/
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tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
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tegra_i2c_ll_write_data(AS3722_SD0VOLTAGE_DATA, I2C_SEND_2_BYTES);
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/*
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* Don't write SDCONTROL - it's already 0x7F, i.e. all SDs enabled.
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* tegra_i2c_ll_write_data(AS3722_SD0CONTROL_DATA, I2C_SEND_2_BYTES);
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*/
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udelay(10 * 1000);
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debug("%s: Setting VDD_GPU to 1.0V via AS3722 reg 6/4D\n", __func__);
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/*
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* Bring up VDD_GPU via the AS3722 PMIC on the PWR I2C bus.
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* First set VDD to 1.0V, then enable the VDD regulator.
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*/
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tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
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tegra_i2c_ll_write_data(AS3722_SD6VOLTAGE_DATA, I2C_SEND_2_BYTES);
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/*
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* Don't write SDCONTROL - it's already 0x7F, i.e. all SDs enabled.
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* tegra_i2c_ll_write_data(AS3722_SD6CONTROL_DATA, I2C_SEND_2_BYTES);
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*/
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udelay(10 * 1000);
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debug("%s: Set VPP_FUSE to 1.2V via AS3722 reg 0x12/4E\n", __func__);
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/*
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* Bring up VPP_FUSE via the AS3722 PMIC on the PWR I2C bus.
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* First set VDD to 1.2V, then enable the VDD regulator.
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*/
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tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
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tegra_i2c_ll_write_data(AS3722_LDO2VOLTAGE_DATA, I2C_SEND_2_BYTES);
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/*
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* Don't write LDCONTROL - it's already 0xFF, i.e. all LDOs enabled.
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* tegra_i2c_ll_write_data(AS3722_LDO2CONTROL_DATA, I2C_SEND_2_BYTES);
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*/
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udelay(10 * 1000);
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debug("%s: Set VDD_SDMMC1 to 3.3V via AS3722 reg 0x11/4E\n", __func__);
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/*
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* Bring up VDD_SDMMC1 via the AS3722 PMIC on the PWR I2C bus.
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* First set it to value closest to 3.3V, then enable the regulator
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*
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* NOTE: We do this early because doing it later seems to hose the CPU
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* power rail/partition startup. Need to debug.
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*/
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tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
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tegra_i2c_ll_write_data(AS3722_LDO1VOLTAGE_DATA, I2C_SEND_2_BYTES);
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/*
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* Don't write LDCONTROL - it's already 0xFF, i.e. all LDOs enabled.
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* tegra_i2c_ll_write_data(AS3722_LDO1CONTROL_DATA, I2C_SEND_2_BYTES);
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*/
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udelay(10 * 1000);
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debug("%s: Set VDD_SDMMC3 to 3.3V via AS3722 reg 0x16/4E\n", __func__);
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/*
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* Bring up VDD_SDMMC3 via the AS3722 PMIC on the PWR I2C bus.
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* First set it to bypass 3.3V straight thru, then enable the regulator
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*
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* NOTE: We do this early because doing it later seems to hose the CPU
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* power rail/partition startup. Need to debug.
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*/
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tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
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tegra_i2c_ll_write_data(AS3722_LDO6VOLTAGE_DATA, I2C_SEND_2_BYTES);
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/*
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* Don't write LDCONTROL - it's already 0xFF, i.e. all LDOs enabled.
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* tegra_i2c_ll_write_data(AS3722_LDO6CONTROL_DATA, I2C_SEND_2_BYTES);
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*/
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udelay(10 * 1000);
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}
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