mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-05 10:46:15 +09:00
7c0a4b7955
This adds support for the omap4 reboot mode mechanism and exports the reboot mode via an environment variable, that is used in the boot command to make it possible to boot from the recovery partition or fastboot. Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
99 lines
3.8 KiB
C
99 lines
3.8 KiB
C
/*
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* Amazon Kindle Fire (first generation) codename kc1 config
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*
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* Copyright (C) 2016 Paul Kocialkowski <contact@paulk.fr>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _KC1_H_
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#define _KC1_H_
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#include <asm/arch/mux_omap4.h>
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#define KC1_GPIO_USB_ID 52
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#define KC1_GPIO_MBID1 173
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#define KC1_GPIO_MBID0 174
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#define KC1_GPIO_MBID3 177
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#define KC1_GPIO_MBID2 178
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const struct pad_conf_entry core_padconf_array[] = {
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/* GPMC */
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{ GPMC_AD0, (IEN | PTU | M1) }, /* sdmmc2_dat0 */
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{ GPMC_AD1, (IEN | PTU | M1) }, /* sdmmc2_dat1 */
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{ GPMC_AD2, (IEN | PTU | M1) }, /* sdmmc2_dat2 */
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{ GPMC_AD3, (IEN | PTU | M1) }, /* sdmmc2_dat3 */
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{ GPMC_AD4, (IEN | PTU | M1) }, /* sdmmc2_dat4 */
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{ GPMC_AD5, (IEN | PTU | M1) }, /* sdmmc2_dat5 */
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{ GPMC_AD6, (IEN | PTU | M1) }, /* sdmmc2_dat6 */
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{ GPMC_AD7, (IEN | PTU | M1) }, /* sdmmc2_dat7 */
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{ GPMC_NOE, (IEN | PTU | M1) }, /* sdmmc2_clk */
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{ GPMC_NWE, (IEN | PTU | M1) }, /* sdmmc2_cmd */
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{ GPMC_NCS2, (IEN | PTD | M3) }, /* gpio_52 */
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/* CAM */
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{ CAM_SHUTTER, (IDIS | DIS | M7) }, /* safe_mode */
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{ CAM_STROBE, (IDIS | DIS | M7) }, /* safe_mode */
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{ CAM_GLOBALRESET, (IDIS | DIS | M7) }, /* safe_mode */
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/* HDQ */
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{ HDQ_SIO, (IDIS | DIS | M7) }, /* safe_mode */
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/* I2C1 */
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{ I2C1_SCL, (IEN | PTU | M0) }, /* i2c1_scl */
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{ I2C1_SDA, (IEN | PTU | M0) }, /* i2c1_sda */
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/* I2C2 */
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{ I2C2_SCL, (IEN | PTU | M0) }, /* i2c2_scl */
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{ I2C2_SDA, (IEN | PTU | M0) }, /* i2c2_sda */
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/* I2C3 */
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{ I2C3_SCL, (IEN | PTU | M0) }, /* i2c3_scl */
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{ I2C3_SDA, (IEN | PTU | M0) }, /* i2c3_sda */
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/* I2C4 */
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{ I2C4_SCL, (IEN | PTU | M0) }, /* i2c4_scl */
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{ I2C4_SDA, (IEN | PTU | M0) }, /* i2c4_sda */
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/* MCSPI1 */
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{ MCSPI1_CLK, (IDIS | DIS | M7) }, /* safe_mode */
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{ MCSPI1_SOMI, (IDIS | DIS | M7) }, /* safe_mode */
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{ MCSPI1_SIMO, (IDIS | DIS | M7) }, /* safe_mode */
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{ MCSPI1_CS0, (IDIS | DIS | M7) }, /* safe_mode */
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{ MCSPI1_CS1, (IDIS | DIS | M7) }, /* safe_mode */
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{ MCSPI1_CS2, (IDIS | DIS | M7) }, /* safe_mode */
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{ MCSPI1_CS3, (IDIS | DIS | M7) }, /* safe_mode */
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/* UART3 */
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{ UART3_CTS_RCTX, (IDIS | DIS | M7) }, /* safe_mode */
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{ UART3_RTS_SD, (IDIS | DIS | M7) }, /* safe_mode */
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{ UART3_RX_IRRX, (IEN | DIS | M0) }, /* uart3_rx_irrx */
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{ UART3_TX_IRTX, (IDIS | DIS | M0) }, /* uart3_tx_irtx */
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/* SDMMC5 */
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{ SDMMC5_CLK, (IEN | PTU | M0) }, /* sdmmc5_clk */
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{ SDMMC5_CMD, (IEN | PTU | M0) }, /* sdmmc5_cmd */
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{ SDMMC5_DAT0, (IEN | PTU | M0) }, /* sdmmc5_dat0 */
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{ SDMMC5_DAT1, (IEN | PTU | M0) }, /* sdmmc5_dat1 */
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{ SDMMC5_DAT2, (IEN | PTU | M0) }, /* sdmmc5_dat2 */
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{ SDMMC5_DAT3, (IEN | PTU | M0) }, /* sdmmc5_dat3 */
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/* MCSPI4 */
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{ MCSPI4_CLK, (IEN | DIS | M0) }, /* mcspi4_clk */
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{ MCSPI4_SIMO, (IEN | DIS | M0) }, /* mcspi4_simo */
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{ MCSPI4_SOMI, (IEN | DIS | M0) }, /* mcspi4_somi */
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{ MCSPI4_CS0, (IEN | PTD | M0) }, /* mcspi4_cs0 */
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/* UART4 */
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{ UART4_RX, (IDIS | DIS | M4) }, /* gpio_155 */
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{ UART4_TX, (IDIS | DIS | M7) }, /* safe_mode */
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/* UNIPRO */
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{ UNIPRO_TX0, (IDIS | DIS | M7) }, /* safe_mode */
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{ UNIPRO_TY0, (IDIS | DIS | M7) }, /* safe_mode */
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{ UNIPRO_TX1, (IEN | DIS | M3) }, /* gpio_173 */
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{ UNIPRO_TY1, (IEN | DIS | M3) }, /* gpio_174 */
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{ UNIPRO_TX2, (IDIS | DIS | M7) }, /* safe_mode */
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{ UNIPRO_TY2, (IDIS | DIS | M7) }, /* safe_mode */
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{ UNIPRO_RX0, (IEN | DIS | M3) }, /* gpio_175 */
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{ UNIPRO_RY0, (IEN | DIS | M3) }, /* gpio_176 */
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{ UNIPRO_RX1, (IEN | DIS | M3) }, /* gpio_177 */
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{ UNIPRO_RY1, (IEN | DIS | M3) }, /* gpio_178 */
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{ UNIPRO_RX2, (IDIS | DIS | M7) }, /* safe_mode */
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{ UNIPRO_RY2, (IDIS | DIS | M7) }, /* safe_mode */
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/* USBA0_OTG */
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{ USBA0_OTG_CE, (IDIS | PTD | M0) }, /* usba0_otg_ce */
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{ USBA0_OTG_DP, (IEN | DIS | M0) }, /* usba0_otg_dp */
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{ USBA0_OTG_DM, (IEN | DIS | M0) }, /* usba0_otg_dm */
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};
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#endif
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