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https://github.com/brain-hackers/u-boot-brain
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00f7bbae92
The MPC837xE-MDS board's CPLD can auto-detect if the board is on the PIB, standalone or acting as a PCI agent. User's Guide says: - When the CPLD recognizes its location on the PIB it automatically configures RCW to the PCI Host. - If the CPLD fails to recognize its location then it is automatically configured as an Agent and the PCI is configured to an external arbiter. This sounds good. Though in the standalone setup the CPLD sets PCI_HOST flag (it's ok, we can't act as PCI agents since we receive CLKIN, not PCICLK), but the CPLD doesn't set the ARBITER_ENABLE flag, and without any arbiter bad things will happen (here the board hangs during any config space reads). In this situation we must disable the PCI. And in case of anybody really want to use an external arbiter, we provide "pci_external_aribter" environment variable. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
69 lines
1.7 KiB
C
69 lines
1.7 KiB
C
/*
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* Copyright (C) 2007 Freescale Semiconductor, Inc.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*/
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#include <asm/mmu.h>
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#include <asm/io.h>
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#include <common.h>
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#include <mpc83xx.h>
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#include <pci.h>
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#include <i2c.h>
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#include <asm/fsl_i2c.h>
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#if defined(CONFIG_PCI)
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static struct pci_region pci_regions[] = {
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{
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bus_start: CONFIG_SYS_PCI_MEM_BASE,
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phys_start: CONFIG_SYS_PCI_MEM_PHYS,
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size: CONFIG_SYS_PCI_MEM_SIZE,
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flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
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},
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{
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bus_start: CONFIG_SYS_PCI_MMIO_BASE,
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phys_start: CONFIG_SYS_PCI_MMIO_PHYS,
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size: CONFIG_SYS_PCI_MMIO_SIZE,
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flags: PCI_REGION_MEM
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},
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{
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bus_start: CONFIG_SYS_PCI_IO_BASE,
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phys_start: CONFIG_SYS_PCI_IO_PHYS,
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size: CONFIG_SYS_PCI_IO_SIZE,
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flags: PCI_REGION_IO
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}
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};
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void pci_init_board(void)
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{
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volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
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volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
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volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
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struct pci_region *reg[] = { pci_regions };
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if (board_pci_host_broken())
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return;
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/* Enable all 5 PCI_CLK_OUTPUTS */
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clk->occr |= 0xf8000000;
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udelay(2000);
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/* Configure PCI Local Access Windows */
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pci_law[0].bar = CONFIG_SYS_PCI_MEM_PHYS & LAWBAR_BAR;
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pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB;
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pci_law[1].bar = CONFIG_SYS_PCI_IO_PHYS & LAWBAR_BAR;
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pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB;
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udelay(2000);
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mpc83xx_pci_init(1, reg, 0);
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}
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#endif /* CONFIG_PCI */
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