mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
ae5f943ba8
The 8572 DDR erratum1: DDR controller may enter an illegal state when operating in 32-bit bus mode with 4-beat bursts. Description: When operating with a 32-bit bus, it is recommended that DDR_SDRAM_CFG[8_BE] is cleared when DDR2 memories are used. This forces the DDR controller to use 4-beat bursts when communicating to the DRAMs. However, an issue exists that could lead to data corruption when the DDR controller is in 32-bit bus mode while using 4-beat bursts. Projected Impact: If the DDR controller is operating in 32-bit bus mode with 4-beat bursts, then the controller may enter into a bad state. All subsequent reads from memory is corrupted. Four-beat bursts with a 32-bit bus only is used with DDR2 memories. Therefore, this erratum does not affect DDR3 mode. Work Arounds: To work around this issue, software must set DEBUG_1[31] in DDR memory mapped space (CCSRBAR offset + 0x2f00 for DDR_1 and CCSRBAR offset + 0x6f00 for DDR_2). Currenlty, the code is using incorrect register DDR_SDRAM_CFG_2 as condition, but it should be DDR_SDRAM_CFG register. Signed-off-by: Dave Liu <daveliu@freescale.com> |
||
|---|---|---|
| .. | ||
| 74xx_7xx | ||
| arm_intcm | ||
| arm720t | ||
| arm920t | ||
| arm925t | ||
| arm926ejs | ||
| arm946es | ||
| arm1136 | ||
| arm1176 | ||
| at32ap | ||
| blackfin | ||
| i386 | ||
| ixp | ||
| leon2 | ||
| leon3 | ||
| lh7a40x | ||
| mcf52x2 | ||
| mcf523x | ||
| mcf532x | ||
| mcf547x_8x | ||
| mcf5227x | ||
| mcf5445x | ||
| microblaze | ||
| mips | ||
| mpc5xx | ||
| mpc5xxx | ||
| mpc8xx | ||
| mpc8xxx/ddr | ||
| mpc83xx | ||
| mpc85xx | ||
| mpc86xx | ||
| mpc512x | ||
| mpc824x | ||
| mpc8220 | ||
| mpc8260 | ||
| nios | ||
| nios2 | ||
| ppc4xx | ||
| pxa | ||
| s3c44b0 | ||
| sa1100 | ||
| sh2 | ||
| sh3 | ||
| sh4 | ||