mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-19 08:28:51 +09:00
![Marek Szyprowski](/assets/img/avatar_default.png)
Odroid HC1 board is based on Odroid XU4 board, but it has no HDMI, no eMMC, no build-in USB3.0 hub, no extension port pins, and no GPIO button. USB3.0 ports are used for build-in JMicron USB to SATA bridge and Gigabit R8152 ethernet chips. HC1 uses only passive cooling. This patch also updates Odroid's ADCmax array and reduces ADC tolerance to 1% to ensure that XU4 and HC1 revisions are properly detected. I've tested this with XU3, XU3-lite, XU4 and HC1 boards. In case of my test boards I got following values from ADC register: 372, 370, 1281 and 1313. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Reviewed-by: Lukasz Majewski <lukma@denx.de> Tested-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
212 lines
4.2 KiB
C
212 lines
4.2 KiB
C
/*
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* Copyright (C) 2012 Samsung Electronics
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <dm.h>
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#include <dwc3-uboot.h>
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#include <fdtdec.h>
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#include <asm/io.h>
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#include <errno.h>
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#include <i2c.h>
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#include <mmc.h>
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#include <netdev.h>
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#include <samsung-usb-phy-uboot.h>
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#include <spi.h>
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#include <usb.h>
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#include <video_bridge.h>
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#include <asm/gpio.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/dwmmc.h>
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#include <asm/arch/mmc.h>
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#include <asm/arch/pinmux.h>
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#include <asm/arch/power.h>
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#include <asm/arch/sromc.h>
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#include <power/pmic.h>
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#include <power/max77686_pmic.h>
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#include <power/regulator.h>
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#include <power/s2mps11.h>
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#include <power/s5m8767.h>
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#include <samsung/exynos5-dt-types.h>
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#include <samsung/misc.h>
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#include <tmu.h>
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DECLARE_GLOBAL_DATA_PTR;
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static void board_enable_audio_codec(void)
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{
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int node, ret;
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struct gpio_desc en_gpio;
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node = fdtdec_next_compatible(gd->fdt_blob, 0,
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COMPAT_SAMSUNG_EXYNOS5_SOUND);
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if (node <= 0)
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return;
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ret = gpio_request_by_name_nodev(offset_to_ofnode(node),
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"codec-enable-gpio", 0, &en_gpio,
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GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
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if (ret == -FDT_ERR_NOTFOUND)
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return;
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/* Turn on the GPIO which connects to the codec's "enable" line. */
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gpio_set_pull(gpio_get_number(&en_gpio), S5P_GPIO_PULL_NONE);
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#ifdef CONFIG_SOUND_MAX98095
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/* Enable MAX98095 Codec */
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gpio_request(EXYNOS5_GPIO_X17, "max98095_enable");
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gpio_direction_output(EXYNOS5_GPIO_X17, 1);
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gpio_set_pull(EXYNOS5_GPIO_X17, S5P_GPIO_PULL_NONE);
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#endif
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}
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int exynos_init(void)
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{
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board_enable_audio_codec();
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return 0;
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}
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static int exynos_set_regulator(const char *name, uint uv)
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{
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struct udevice *dev;
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int ret;
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ret = regulator_get_by_platname(name, &dev);
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if (ret) {
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debug("%s: Cannot find regulator %s\n", __func__, name);
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return ret;
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}
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ret = regulator_set_value(dev, uv);
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if (ret) {
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debug("%s: Cannot set regulator %s\n", __func__, name);
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return ret;
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}
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return 0;
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}
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int exynos_power_init(void)
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{
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struct udevice *dev;
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int ret;
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ret = pmic_get("max77686", &dev);
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if (!ret) {
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/* TODO(sjg@chromium.org): Move into the clock/pmic API */
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ret = pmic_clrsetbits(dev, MAX77686_REG_PMIC_32KHZ, 0,
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MAX77686_32KHCP_EN);
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if (ret)
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return ret;
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ret = pmic_clrsetbits(dev, MAX77686_REG_PMIC_BBAT, 0,
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MAX77686_BBCHOSTEN | MAX77686_BBCVS_3_5V);
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if (ret)
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return ret;
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} else {
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ret = pmic_get("s5m8767-pmic", &dev);
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/* TODO(sjg@chromium.org): Use driver model to access clock */
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#ifdef CONFIG_PMIC_S5M8767
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if (!ret)
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s5m8767_enable_32khz_cp(dev);
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#endif
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}
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if (ret == -ENODEV)
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return 0;
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ret = regulators_enable_boot_on(false);
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if (ret)
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return ret;
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ret = exynos_set_regulator("vdd_mif", 1100000);
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if (ret)
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return ret;
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ret = exynos_set_regulator("vdd_arm", 1300000);
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if (ret)
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return ret;
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ret = exynos_set_regulator("vdd_int", 1012500);
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if (ret)
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return ret;
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ret = exynos_set_regulator("vdd_g3d", 1200000);
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if (ret)
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return ret;
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return 0;
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}
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int board_get_revision(void)
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{
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return 0;
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}
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#ifdef CONFIG_USB_DWC3
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static struct dwc3_device dwc3_device_data = {
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.maximum_speed = USB_SPEED_SUPER,
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.base = 0x12400000,
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.dr_mode = USB_DR_MODE_PERIPHERAL,
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.index = 0,
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};
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int usb_gadget_handle_interrupts(void)
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{
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dwc3_uboot_handle_interrupt(0);
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return 0;
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}
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int board_usb_init(int index, enum usb_init_type init)
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{
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struct exynos_usb3_phy *phy = (struct exynos_usb3_phy *)
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samsung_get_base_usb3_phy();
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if (!phy) {
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pr_err("usb3 phy not supported");
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return -ENODEV;
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}
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set_usbdrd_phy_ctrl(POWER_USB_DRD_PHY_CTRL_EN);
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exynos5_usb3_phy_init(phy);
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return dwc3_uboot_init(&dwc3_device_data);
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}
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#endif
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#ifdef CONFIG_SET_DFU_ALT_INFO
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char *get_dfu_alt_system(char *interface, char *devstr)
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{
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char *info = "Not supported!";
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if (board_is_odroidxu4() || board_is_odroidhc1())
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return info;
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return env_get("dfu_alt_system");
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}
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char *get_dfu_alt_boot(char *interface, char *devstr)
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{
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char *info = "Not supported!";
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struct mmc *mmc;
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char *alt_boot;
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int dev_num;
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if (board_is_odroidxu4() || board_is_odroidhc1())
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return info;
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dev_num = simple_strtoul(devstr, NULL, 10);
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mmc = find_mmc_device(dev_num);
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if (!mmc)
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return NULL;
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if (mmc_init(mmc))
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return NULL;
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if (IS_SD(mmc))
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alt_boot = CONFIG_DFU_ALT_BOOT_SD;
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else
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alt_boot = CONFIG_DFU_ALT_BOOT_EMMC;
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return alt_boot;
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}
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#endif
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