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https://github.com/brain-hackers/u-boot-brain
synced 2024-08-22 01:48:52 +09:00
![Łukasz Majewski](/assets/img/avatar_default.png)
In the MAX8997, LDO regulators needs to preserve previously set voltage values. Signed-off-by: Lukasz Majewski <l.majewski@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
531 lines
13 KiB
C
531 lines
13 KiB
C
/*
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* Copyright (C) 2011 Samsung Electronics
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* Heungjun Kim <riverful.kim@samsung.com>
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* Kyungmin Park <kyungmin.park@samsung.com>
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* Donghwa Lee <dh09.lee@samsung.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <lcd.h>
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#include <asm/io.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/gpio.h>
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#include <asm/arch/mmc.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/clk.h>
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#include <asm/arch/mipi_dsim.h>
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#include <asm/arch/watchdog.h>
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#include <asm/arch/power.h>
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#include <pmic.h>
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#include <usb/s3c_udc.h>
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#include <max8997_pmic.h>
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#include <libtizen.h>
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#include "setup.h"
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DECLARE_GLOBAL_DATA_PTR;
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unsigned int board_rev;
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#ifdef CONFIG_REVISION_TAG
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u32 get_board_rev(void)
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{
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return board_rev;
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}
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#endif
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static void check_hw_revision(void);
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static int hwrevision(int rev)
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{
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return (board_rev & 0xf) == rev;
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}
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int board_init(void)
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{
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gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
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check_hw_revision();
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printf("HW Revision:\t0x%x\n", board_rev);
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#if defined(CONFIG_PMIC)
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pmic_init();
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#endif
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return 0;
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}
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int dram_init(void)
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{
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gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE) +
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get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE);
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return 0;
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}
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void dram_init_banksize(void)
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{
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gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
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gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
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gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
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gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
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}
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static unsigned int get_hw_revision(void)
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{
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struct exynos4_gpio_part1 *gpio =
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(struct exynos4_gpio_part1 *)samsung_get_base_gpio_part1();
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int hwrev = 0;
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int i;
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/* hw_rev[3:0] == GPE1[3:0] */
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for (i = 0; i < 4; i++) {
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s5p_gpio_cfg_pin(&gpio->e1, i, GPIO_INPUT);
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s5p_gpio_set_pull(&gpio->e1, i, GPIO_PULL_NONE);
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}
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udelay(1);
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for (i = 0; i < 4; i++)
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hwrev |= (s5p_gpio_get_value(&gpio->e1, i) << i);
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debug("hwrev 0x%x\n", hwrev);
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return hwrev;
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}
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static void check_hw_revision(void)
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{
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int hwrev;
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hwrev = get_hw_revision();
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board_rev |= hwrev;
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}
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#ifdef CONFIG_DISPLAY_BOARDINFO
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int checkboard(void)
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{
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puts("Board:\tTRATS\n");
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return 0;
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}
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#endif
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#ifdef CONFIG_GENERIC_MMC
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int board_mmc_init(bd_t *bis)
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{
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struct exynos4_gpio_part2 *gpio =
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(struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2();
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int i, err;
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/* eMMC_EN: SD_0_CDn: GPK0[2] Output High */
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s5p_gpio_direction_output(&gpio->k0, 2, 1);
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s5p_gpio_set_pull(&gpio->k0, 2, GPIO_PULL_NONE);
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/*
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* eMMC GPIO:
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* SDR 8-bit@48MHz at MMC0
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* GPK0[0] SD_0_CLK(2)
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* GPK0[1] SD_0_CMD(2)
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* GPK0[2] SD_0_CDn -> Not used
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* GPK0[3:6] SD_0_DATA[0:3](2)
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* GPK1[3:6] SD_0_DATA[0:3](3)
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*
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* DDR 4-bit@26MHz at MMC4
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* GPK0[0] SD_4_CLK(3)
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* GPK0[1] SD_4_CMD(3)
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* GPK0[2] SD_4_CDn -> Not used
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* GPK0[3:6] SD_4_DATA[0:3](3)
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* GPK1[3:6] SD_4_DATA[4:7](4)
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*/
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for (i = 0; i < 7; i++) {
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if (i == 2)
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continue;
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/* GPK0[0:6] special function 2 */
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s5p_gpio_cfg_pin(&gpio->k0, i, 0x2);
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/* GPK0[0:6] pull disable */
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s5p_gpio_set_pull(&gpio->k0, i, GPIO_PULL_NONE);
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/* GPK0[0:6] drv 4x */
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s5p_gpio_set_drv(&gpio->k0, i, GPIO_DRV_4X);
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}
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for (i = 3; i < 7; i++) {
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/* GPK1[3:6] special function 3 */
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s5p_gpio_cfg_pin(&gpio->k1, i, 0x3);
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/* GPK1[3:6] pull disable */
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s5p_gpio_set_pull(&gpio->k1, i, GPIO_PULL_NONE);
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/* GPK1[3:6] drv 4x */
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s5p_gpio_set_drv(&gpio->k1, i, GPIO_DRV_4X);
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}
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/*
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* MMC device init
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* mmc0 : eMMC (8-bit buswidth)
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* mmc2 : SD card (4-bit buswidth)
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*/
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err = s5p_mmc_init(0, 8);
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/* T-flash detect */
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s5p_gpio_cfg_pin(&gpio->x3, 4, 0xf);
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s5p_gpio_set_pull(&gpio->x3, 4, GPIO_PULL_UP);
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/*
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* Check the T-flash detect pin
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* GPX3[4] T-flash detect pin
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*/
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if (!s5p_gpio_get_value(&gpio->x3, 4)) {
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/*
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* SD card GPIO:
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* GPK2[0] SD_2_CLK(2)
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* GPK2[1] SD_2_CMD(2)
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* GPK2[2] SD_2_CDn -> Not used
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* GPK2[3:6] SD_2_DATA[0:3](2)
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*/
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for (i = 0; i < 7; i++) {
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if (i == 2)
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continue;
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/* GPK2[0:6] special function 2 */
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s5p_gpio_cfg_pin(&gpio->k2, i, 0x2);
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/* GPK2[0:6] pull disable */
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s5p_gpio_set_pull(&gpio->k2, i, GPIO_PULL_NONE);
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/* GPK2[0:6] drv 4x */
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s5p_gpio_set_drv(&gpio->k2, i, GPIO_DRV_4X);
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}
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err = s5p_mmc_init(2, 4);
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}
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return err;
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}
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#endif
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#ifdef CONFIG_USB_GADGET
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static int s5pc210_phy_control(int on)
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{
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int ret = 0;
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u32 val = 0;
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struct pmic *p = get_pmic();
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if (pmic_probe(p))
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return -1;
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if (on) {
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ret |= pmic_set_output(p, MAX8997_REG_SAFEOUTCTRL,
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ENSAFEOUT1, LDO_ON);
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ret |= pmic_reg_read(p, MAX8997_REG_LDO3CTRL, &val);
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ret |= pmic_reg_write(p, MAX8997_REG_LDO3CTRL, EN_LDO | val);
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ret |= pmic_reg_read(p, MAX8997_REG_LDO8CTRL, &val);
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ret |= pmic_reg_write(p, MAX8997_REG_LDO8CTRL, EN_LDO | val);
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} else {
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ret |= pmic_reg_read(p, MAX8997_REG_LDO8CTRL, &val);
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ret |= pmic_reg_write(p, MAX8997_REG_LDO8CTRL, DIS_LDO | val);
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ret |= pmic_reg_read(p, MAX8997_REG_LDO3CTRL, &val);
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ret |= pmic_reg_write(p, MAX8997_REG_LDO3CTRL, DIS_LDO | val);
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ret |= pmic_set_output(p, MAX8997_REG_SAFEOUTCTRL,
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ENSAFEOUT1, LDO_OFF);
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}
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if (ret) {
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puts("MAX8997 LDO setting error!\n");
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return -1;
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}
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return 0;
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}
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struct s3c_plat_otg_data s5pc210_otg_data = {
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.phy_control = s5pc210_phy_control,
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.regs_phy = EXYNOS4_USBPHY_BASE,
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.regs_otg = EXYNOS4_USBOTG_BASE,
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.usb_phy_ctrl = EXYNOS4_USBPHY_CONTROL,
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.usb_flags = PHY0_SLEEP,
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};
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#endif
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static void pmic_reset(void)
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{
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struct exynos4_gpio_part2 *gpio =
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(struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2();
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s5p_gpio_direction_output(&gpio->x0, 7, 1);
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s5p_gpio_set_pull(&gpio->x2, 7, GPIO_PULL_NONE);
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}
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static void board_clock_init(void)
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{
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struct exynos4_clock *clk =
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(struct exynos4_clock *)samsung_get_base_clock();
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writel(CLK_SRC_CPU_VAL, (unsigned int)&clk->src_cpu);
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writel(CLK_SRC_TOP0_VAL, (unsigned int)&clk->src_top0);
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writel(CLK_SRC_FSYS_VAL, (unsigned int)&clk->src_fsys);
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writel(CLK_SRC_PERIL0_VAL, (unsigned int)&clk->src_peril0);
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writel(CLK_DIV_CPU0_VAL, (unsigned int)&clk->div_cpu0);
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writel(CLK_DIV_CPU1_VAL, (unsigned int)&clk->div_cpu1);
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writel(CLK_DIV_DMC0_VAL, (unsigned int)&clk->div_dmc0);
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writel(CLK_DIV_DMC1_VAL, (unsigned int)&clk->div_dmc1);
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writel(CLK_DIV_LEFTBUS_VAL, (unsigned int)&clk->div_leftbus);
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writel(CLK_DIV_RIGHTBUS_VAL, (unsigned int)&clk->div_rightbus);
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writel(CLK_DIV_TOP_VAL, (unsigned int)&clk->div_top);
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writel(CLK_DIV_FSYS1_VAL, (unsigned int)&clk->div_fsys1);
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writel(CLK_DIV_FSYS2_VAL, (unsigned int)&clk->div_fsys2);
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writel(CLK_DIV_FSYS3_VAL, (unsigned int)&clk->div_fsys3);
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writel(CLK_DIV_PERIL0_VAL, (unsigned int)&clk->div_peril0);
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writel(CLK_DIV_PERIL3_VAL, (unsigned int)&clk->div_peril3);
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writel(PLL_LOCKTIME, (unsigned int)&clk->apll_lock);
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writel(PLL_LOCKTIME, (unsigned int)&clk->mpll_lock);
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writel(PLL_LOCKTIME, (unsigned int)&clk->epll_lock);
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writel(PLL_LOCKTIME, (unsigned int)&clk->vpll_lock);
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writel(APLL_CON1_VAL, (unsigned int)&clk->apll_con1);
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writel(APLL_CON0_VAL, (unsigned int)&clk->apll_con0);
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writel(MPLL_CON1_VAL, (unsigned int)&clk->mpll_con1);
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writel(MPLL_CON0_VAL, (unsigned int)&clk->mpll_con0);
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writel(EPLL_CON1_VAL, (unsigned int)&clk->epll_con1);
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writel(EPLL_CON0_VAL, (unsigned int)&clk->epll_con0);
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writel(VPLL_CON1_VAL, (unsigned int)&clk->vpll_con1);
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writel(VPLL_CON0_VAL, (unsigned int)&clk->vpll_con0);
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writel(CLK_GATE_IP_CAM_VAL, (unsigned int)&clk->gate_ip_cam);
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writel(CLK_GATE_IP_VP_VAL, (unsigned int)&clk->gate_ip_tv);
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writel(CLK_GATE_IP_MFC_VAL, (unsigned int)&clk->gate_ip_mfc);
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writel(CLK_GATE_IP_G3D_VAL, (unsigned int)&clk->gate_ip_g3d);
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writel(CLK_GATE_IP_IMAGE_VAL, (unsigned int)&clk->gate_ip_image);
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writel(CLK_GATE_IP_LCD0_VAL, (unsigned int)&clk->gate_ip_lcd0);
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writel(CLK_GATE_IP_LCD1_VAL, (unsigned int)&clk->gate_ip_lcd1);
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writel(CLK_GATE_IP_FSYS_VAL, (unsigned int)&clk->gate_ip_fsys);
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writel(CLK_GATE_IP_GPS_VAL, (unsigned int)&clk->gate_ip_gps);
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writel(CLK_GATE_IP_PERIL_VAL, (unsigned int)&clk->gate_ip_peril);
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writel(CLK_GATE_IP_PERIR_VAL, (unsigned int)&clk->gate_ip_perir);
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writel(CLK_GATE_BLOCK_VAL, (unsigned int)&clk->gate_block);
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}
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static void board_power_init(void)
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{
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struct exynos4_power *pwr =
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(struct exynos4_power *)samsung_get_base_power();
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/* PS HOLD */
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writel(EXYNOS4_PS_HOLD_CON_VAL, (unsigned int)&pwr->ps_hold_control);
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/* Set power down */
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writel(0, (unsigned int)&pwr->cam_configuration);
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writel(0, (unsigned int)&pwr->tv_configuration);
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writel(0, (unsigned int)&pwr->mfc_configuration);
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writel(0, (unsigned int)&pwr->g3d_configuration);
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writel(0, (unsigned int)&pwr->lcd1_configuration);
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writel(0, (unsigned int)&pwr->gps_configuration);
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writel(0, (unsigned int)&pwr->gps_alive_configuration);
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}
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static void board_uart_init(void)
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{
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struct exynos4_gpio_part1 *gpio1 =
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(struct exynos4_gpio_part1 *)samsung_get_base_gpio_part1();
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struct exynos4_gpio_part2 *gpio2 =
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(struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2();
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int i;
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/*
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* UART2 GPIOs
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* GPA1CON[0] = UART_2_RXD(2)
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* GPA1CON[1] = UART_2_TXD(2)
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* GPA1CON[2] = I2C_3_SDA (3)
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* GPA1CON[3] = I2C_3_SCL (3)
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*/
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for (i = 0; i < 4; i++) {
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s5p_gpio_set_pull(&gpio1->a1, i, GPIO_PULL_NONE);
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s5p_gpio_cfg_pin(&gpio1->a1, i, GPIO_FUNC((i > 1) ? 0x3 : 0x2));
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}
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/* UART_SEL GPY4[7] (part2) at EXYNOS4 */
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s5p_gpio_set_pull(&gpio2->y4, 7, GPIO_PULL_UP);
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s5p_gpio_direction_output(&gpio2->y4, 7, 1);
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}
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int board_early_init_f(void)
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{
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wdt_stop();
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pmic_reset();
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board_clock_init();
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board_uart_init();
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board_power_init();
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return 0;
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}
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static void lcd_reset(void)
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{
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struct exynos4_gpio_part2 *gpio2 =
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(struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2();
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s5p_gpio_direction_output(&gpio2->y4, 5, 1);
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udelay(10000);
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s5p_gpio_direction_output(&gpio2->y4, 5, 0);
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udelay(10000);
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s5p_gpio_direction_output(&gpio2->y4, 5, 1);
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}
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static int lcd_power(void)
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{
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int ret = 0;
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struct pmic *p = get_pmic();
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if (pmic_probe(p))
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return 0;
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/* LDO15 voltage: 2.2v */
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ret |= pmic_reg_write(p, MAX8997_REG_LDO15CTRL, 0x1c | EN_LDO);
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/* LDO13 voltage: 3.0v */
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ret |= pmic_reg_write(p, MAX8997_REG_LDO13CTRL, 0x2c | EN_LDO);
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if (ret) {
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puts("MAX8997 LDO setting error!\n");
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return -1;
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}
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return 0;
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}
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static struct mipi_dsim_config dsim_config = {
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.e_interface = DSIM_VIDEO,
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.e_virtual_ch = DSIM_VIRTUAL_CH_0,
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.e_pixel_format = DSIM_24BPP_888,
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.e_burst_mode = DSIM_BURST_SYNC_EVENT,
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.e_no_data_lane = DSIM_DATA_LANE_4,
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.e_byte_clk = DSIM_PLL_OUT_DIV8,
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.hfp = 1,
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.p = 3,
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.m = 120,
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.s = 1,
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/* D-PHY PLL stable time spec :min = 200usec ~ max 400usec */
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.pll_stable_time = 500,
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/* escape clk : 10MHz */
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.esc_clk = 20 * 1000000,
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/* stop state holding counter after bta change count 0 ~ 0xfff */
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.stop_holding_cnt = 0x7ff,
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/* bta timeout 0 ~ 0xff */
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.bta_timeout = 0xff,
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/* lp rx timeout 0 ~ 0xffff */
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.rx_timeout = 0xffff,
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};
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static struct exynos_platform_mipi_dsim s6e8ax0_platform_data = {
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.lcd_panel_info = NULL,
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.dsim_config = &dsim_config,
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};
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static struct mipi_dsim_lcd_device mipi_lcd_device = {
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.name = "s6e8ax0",
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.id = -1,
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.bus_id = 0,
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.platform_data = (void *)&s6e8ax0_platform_data,
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};
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static int mipi_power(void)
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{
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int ret = 0;
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struct pmic *p = get_pmic();
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if (pmic_probe(p))
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return 0;
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/* LDO3 voltage: 1.1v */
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ret |= pmic_reg_write(p, MAX8997_REG_LDO3CTRL, 0x6 | EN_LDO);
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/* LDO4 voltage: 1.8v */
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ret |= pmic_reg_write(p, MAX8997_REG_LDO4CTRL, 0x14 | EN_LDO);
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if (ret) {
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puts("MAX8997 LDO setting error!\n");
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return -1;
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}
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return 0;
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}
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vidinfo_t panel_info = {
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.vl_freq = 60,
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.vl_col = 720,
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.vl_row = 1280,
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.vl_width = 720,
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.vl_height = 1280,
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.vl_clkp = CONFIG_SYS_HIGH,
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.vl_hsp = CONFIG_SYS_LOW,
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.vl_vsp = CONFIG_SYS_LOW,
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.vl_dp = CONFIG_SYS_LOW,
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.vl_bpix = 5, /* Bits per pixel, 2^5 = 32 */
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/* s6e8ax0 Panel infomation */
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.vl_hspw = 5,
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.vl_hbpd = 10,
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.vl_hfpd = 10,
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.vl_vspw = 2,
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.vl_vbpd = 1,
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.vl_vfpd = 13,
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.vl_cmd_allow_len = 0xf,
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.win_id = 3,
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.cfg_gpio = NULL,
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.backlight_on = NULL,
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.lcd_power_on = NULL, /* lcd_power_on in mipi dsi driver */
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.reset_lcd = lcd_reset,
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.dual_lcd_enabled = 0,
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.init_delay = 0,
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.power_on_delay = 0,
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.reset_delay = 0,
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.interface_mode = FIMD_RGB_INTERFACE,
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.mipi_enabled = 1,
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};
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void init_panel_info(vidinfo_t *vid)
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{
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vid->logo_on = 1,
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vid->resolution = HD_RESOLUTION,
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vid->rgb_mode = MODE_RGB_P,
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#ifdef CONFIG_TIZEN
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get_tizen_logo_info(vid);
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#endif
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if (hwrevision(2))
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mipi_lcd_device.reverse_panel = 1;
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strcpy(s6e8ax0_platform_data.lcd_panel_name, mipi_lcd_device.name);
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s6e8ax0_platform_data.lcd_power = lcd_power;
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s6e8ax0_platform_data.mipi_power = mipi_power;
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s6e8ax0_platform_data.phy_enable = set_mipi_phy_ctrl;
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s6e8ax0_platform_data.lcd_panel_info = (void *)vid;
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exynos_mipi_dsi_register_lcd_device(&mipi_lcd_device);
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s6e8ax0_init();
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exynos_set_dsim_platform_data(&s6e8ax0_platform_data);
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setenv("lcdinfo", "lcd=s6e8ax0");
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}
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