mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-22 09:58:52 +09:00
![Benoît Thébaudeau](/assets/img/avatar_default.png)
The cache snooping feature of Freescale's eSDHC IP is not available on i.MX, so disable it globally for this architecture. This avoids setting no_snoop for all i.MX boards, and it prevents setting a reserved bit of a reserved register if fsl_esdhc_mmc_init() is used on i.MX, like in arch/arm/cpu/armv7/imx-common/cpu.c/cpu_mmc_init(). Since no_snoop was only used on i.MX, get rid of it BTW. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Andy Fleming <afleming@gmail.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Kim Phillips <kim.phillips@freescale.com>
397 lines
11 KiB
C
397 lines
11 KiB
C
/*
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* (C) Copyright 2010 Freescale Semiconductor, Inc.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/mx5x_pins.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/arch/crm_regs.h>
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#include <asm/arch/iomux.h>
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#include <asm/errno.h>
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#include <asm/imx-common/boot_mode.h>
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#include <netdev.h>
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#include <i2c.h>
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#include <mmc.h>
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#include <fsl_esdhc.h>
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#include <pmic.h>
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#include <fsl_pmic.h>
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#include <asm/gpio.h>
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#include <mc13892.h>
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DECLARE_GLOBAL_DATA_PTR;
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int dram_init(void)
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{
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/* dram_init must store complete ramsize in gd->ram_size */
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gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
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PHYS_SDRAM_1_SIZE);
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return 0;
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}
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static void setup_iomux_uart(void)
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{
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/* UART1 RXD */
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mxc_request_iomux(MX53_PIN_CSI0_D11, IOMUX_CONFIG_ALT2);
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mxc_iomux_set_pad(MX53_PIN_CSI0_D11,
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PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
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PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
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PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU |
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PAD_CTL_ODE_OPENDRAIN_ENABLE);
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mxc_iomux_set_input(MX53_UART1_IPP_UART_RXD_MUX_SELECT_INPUT, 0x1);
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/* UART1 TXD */
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mxc_request_iomux(MX53_PIN_CSI0_D10, IOMUX_CONFIG_ALT2);
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mxc_iomux_set_pad(MX53_PIN_CSI0_D10,
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PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
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PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
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PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU |
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PAD_CTL_ODE_OPENDRAIN_ENABLE);
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}
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static void setup_i2c(unsigned int port_number)
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{
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switch (port_number) {
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case 0:
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/* i2c1 SDA */
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mxc_request_iomux(MX53_PIN_CSI0_D8,
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IOMUX_CONFIG_ALT5 | IOMUX_CONFIG_SION);
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mxc_iomux_set_input(MX53_I2C1_IPP_SDA_IN_SELECT_INPUT,
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INPUT_CTL_PATH0);
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mxc_iomux_set_pad(MX53_PIN_CSI0_D8,
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PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH |
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PAD_CTL_100K_PU | PAD_CTL_HYS_ENABLE |
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PAD_CTL_ODE_OPENDRAIN_ENABLE);
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/* i2c1 SCL */
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mxc_request_iomux(MX53_PIN_CSI0_D9,
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IOMUX_CONFIG_ALT5 | IOMUX_CONFIG_SION);
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mxc_iomux_set_input(MX53_I2C1_IPP_SCL_IN_SELECT_INPUT,
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INPUT_CTL_PATH0);
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mxc_iomux_set_pad(MX53_PIN_CSI0_D9,
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PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH |
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PAD_CTL_100K_PU | PAD_CTL_HYS_ENABLE |
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PAD_CTL_ODE_OPENDRAIN_ENABLE);
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break;
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case 1:
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/* i2c2 SDA */
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mxc_request_iomux(MX53_PIN_KEY_ROW3,
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IOMUX_CONFIG_ALT4 | IOMUX_CONFIG_SION);
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mxc_iomux_set_input(MX53_I2C2_IPP_SDA_IN_SELECT_INPUT,
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INPUT_CTL_PATH0);
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mxc_iomux_set_pad(MX53_PIN_KEY_ROW3,
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PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH |
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PAD_CTL_100K_PU | PAD_CTL_HYS_ENABLE |
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PAD_CTL_ODE_OPENDRAIN_ENABLE);
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/* i2c2 SCL */
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mxc_request_iomux(MX53_PIN_KEY_COL3,
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IOMUX_CONFIG_ALT4 | IOMUX_CONFIG_SION);
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mxc_iomux_set_input(MX53_I2C2_IPP_SCL_IN_SELECT_INPUT,
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INPUT_CTL_PATH0);
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mxc_iomux_set_pad(MX53_PIN_KEY_COL3,
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PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH |
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PAD_CTL_100K_PU | PAD_CTL_HYS_ENABLE |
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PAD_CTL_ODE_OPENDRAIN_ENABLE);
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break;
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default:
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printf("Warning: Wrong I2C port number\n");
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break;
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}
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}
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void power_init(void)
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{
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unsigned int val;
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struct pmic *p;
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pmic_init();
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p = get_pmic();
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/* Set VDDA to 1.25V */
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pmic_reg_read(p, REG_SW_2, &val);
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val &= ~SWX_OUT_MASK;
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val |= SWX_OUT_1_25;
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pmic_reg_write(p, REG_SW_2, val);
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/*
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* Need increase VCC and VDDA to 1.3V
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* according to MX53 IC TO2 datasheet.
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*/
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if (is_soc_rev(CHIP_REV_2_0) == 0) {
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/* Set VCC to 1.3V for TO2 */
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pmic_reg_read(p, REG_SW_1, &val);
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val &= ~SWX_OUT_MASK;
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val |= SWX_OUT_1_30;
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pmic_reg_write(p, REG_SW_1, val);
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/* Set VDDA to 1.3V for TO2 */
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pmic_reg_read(p, REG_SW_2, &val);
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val &= ~SWX_OUT_MASK;
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val |= SWX_OUT_1_30;
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pmic_reg_write(p, REG_SW_2, val);
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}
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}
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static void setup_iomux_fec(void)
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{
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/*FEC_MDIO*/
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mxc_request_iomux(MX53_PIN_FEC_MDIO, IOMUX_CONFIG_ALT0);
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mxc_iomux_set_pad(MX53_PIN_FEC_MDIO,
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PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
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PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
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PAD_CTL_22K_PU | PAD_CTL_ODE_OPENDRAIN_ENABLE);
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mxc_iomux_set_input(MX53_FEC_FEC_MDI_SELECT_INPUT, 0x1);
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/*FEC_MDC*/
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mxc_request_iomux(MX53_PIN_FEC_MDC, IOMUX_CONFIG_ALT0);
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mxc_iomux_set_pad(MX53_PIN_FEC_MDC, PAD_CTL_DRV_HIGH);
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/* FEC RXD1 */
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mxc_request_iomux(MX53_PIN_FEC_RXD1, IOMUX_CONFIG_ALT0);
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mxc_iomux_set_pad(MX53_PIN_FEC_RXD1,
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PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
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/* FEC RXD0 */
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mxc_request_iomux(MX53_PIN_FEC_RXD0, IOMUX_CONFIG_ALT0);
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mxc_iomux_set_pad(MX53_PIN_FEC_RXD0,
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PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
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/* FEC TXD1 */
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mxc_request_iomux(MX53_PIN_FEC_TXD1, IOMUX_CONFIG_ALT0);
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mxc_iomux_set_pad(MX53_PIN_FEC_TXD1, PAD_CTL_DRV_HIGH);
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/* FEC TXD0 */
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mxc_request_iomux(MX53_PIN_FEC_TXD0, IOMUX_CONFIG_ALT0);
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mxc_iomux_set_pad(MX53_PIN_FEC_TXD0, PAD_CTL_DRV_HIGH);
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/* FEC TX_EN */
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mxc_request_iomux(MX53_PIN_FEC_TX_EN, IOMUX_CONFIG_ALT0);
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mxc_iomux_set_pad(MX53_PIN_FEC_TX_EN, PAD_CTL_DRV_HIGH);
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/* FEC TX_CLK */
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mxc_request_iomux(MX53_PIN_FEC_REF_CLK, IOMUX_CONFIG_ALT0);
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mxc_iomux_set_pad(MX53_PIN_FEC_REF_CLK,
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PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
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/* FEC RX_ER */
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mxc_request_iomux(MX53_PIN_FEC_RX_ER, IOMUX_CONFIG_ALT0);
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mxc_iomux_set_pad(MX53_PIN_FEC_RX_ER,
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PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
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/* FEC CRS */
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mxc_request_iomux(MX53_PIN_FEC_CRS_DV, IOMUX_CONFIG_ALT0);
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mxc_iomux_set_pad(MX53_PIN_FEC_CRS_DV,
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PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
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}
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#ifdef CONFIG_FSL_ESDHC
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struct fsl_esdhc_cfg esdhc_cfg[2] = {
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{MMC_SDHC1_BASE_ADDR},
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{MMC_SDHC3_BASE_ADDR},
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};
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int board_mmc_getcd(struct mmc *mmc)
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{
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struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
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int ret;
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mxc_request_iomux(MX53_PIN_EIM_DA11, IOMUX_CONFIG_ALT1);
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gpio_direction_input(IMX_GPIO_NR(3, 11));
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mxc_request_iomux(MX53_PIN_EIM_DA13, IOMUX_CONFIG_ALT1);
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gpio_direction_input(IMX_GPIO_NR(3, 13));
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if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
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ret = !gpio_get_value(IMX_GPIO_NR(3, 13));
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else
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ret = !gpio_get_value(IMX_GPIO_NR(3, 11));
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return ret;
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}
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int board_mmc_init(bd_t *bis)
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{
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u32 index;
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s32 status = 0;
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for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; index++) {
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switch (index) {
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case 0:
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mxc_request_iomux(MX53_PIN_SD1_CMD, IOMUX_CONFIG_ALT0);
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mxc_request_iomux(MX53_PIN_SD1_CLK, IOMUX_CONFIG_ALT0);
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mxc_request_iomux(MX53_PIN_SD1_DATA0,
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IOMUX_CONFIG_ALT0);
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mxc_request_iomux(MX53_PIN_SD1_DATA1,
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IOMUX_CONFIG_ALT0);
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mxc_request_iomux(MX53_PIN_SD1_DATA2,
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IOMUX_CONFIG_ALT0);
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mxc_request_iomux(MX53_PIN_SD1_DATA3,
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IOMUX_CONFIG_ALT0);
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mxc_request_iomux(MX53_PIN_EIM_DA13,
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IOMUX_CONFIG_ALT1);
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mxc_iomux_set_pad(MX53_PIN_SD1_CMD,
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PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
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PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
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PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU);
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mxc_iomux_set_pad(MX53_PIN_SD1_CLK,
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PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
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PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
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PAD_CTL_DRV_HIGH);
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mxc_iomux_set_pad(MX53_PIN_SD1_DATA0,
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PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
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PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
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PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
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mxc_iomux_set_pad(MX53_PIN_SD1_DATA1,
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PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
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PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
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PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
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mxc_iomux_set_pad(MX53_PIN_SD1_DATA2,
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PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
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PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
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PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
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mxc_iomux_set_pad(MX53_PIN_SD1_DATA3,
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PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
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PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
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PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
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break;
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case 1:
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mxc_request_iomux(MX53_PIN_ATA_RESET_B,
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IOMUX_CONFIG_ALT2);
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mxc_request_iomux(MX53_PIN_ATA_IORDY,
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IOMUX_CONFIG_ALT2);
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mxc_request_iomux(MX53_PIN_ATA_DATA8,
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IOMUX_CONFIG_ALT4);
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mxc_request_iomux(MX53_PIN_ATA_DATA9,
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IOMUX_CONFIG_ALT4);
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mxc_request_iomux(MX53_PIN_ATA_DATA10,
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IOMUX_CONFIG_ALT4);
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mxc_request_iomux(MX53_PIN_ATA_DATA11,
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IOMUX_CONFIG_ALT4);
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mxc_request_iomux(MX53_PIN_ATA_DATA0,
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IOMUX_CONFIG_ALT4);
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mxc_request_iomux(MX53_PIN_ATA_DATA1,
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IOMUX_CONFIG_ALT4);
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mxc_request_iomux(MX53_PIN_ATA_DATA2,
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IOMUX_CONFIG_ALT4);
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mxc_request_iomux(MX53_PIN_ATA_DATA3,
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IOMUX_CONFIG_ALT4);
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mxc_request_iomux(MX53_PIN_EIM_DA11,
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IOMUX_CONFIG_ALT1);
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mxc_iomux_set_pad(MX53_PIN_ATA_RESET_B,
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PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
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PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
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PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU);
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mxc_iomux_set_pad(MX53_PIN_ATA_IORDY,
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PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
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PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
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PAD_CTL_DRV_HIGH);
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mxc_iomux_set_pad(MX53_PIN_ATA_DATA8,
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PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
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PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
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PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
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mxc_iomux_set_pad(MX53_PIN_ATA_DATA9,
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PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
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PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
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PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
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mxc_iomux_set_pad(MX53_PIN_ATA_DATA10,
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PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
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PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
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PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
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mxc_iomux_set_pad(MX53_PIN_ATA_DATA11,
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PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
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PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
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PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
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mxc_iomux_set_pad(MX53_PIN_ATA_DATA0,
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PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
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PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
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PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
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mxc_iomux_set_pad(MX53_PIN_ATA_DATA1,
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PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
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PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
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PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
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mxc_iomux_set_pad(MX53_PIN_ATA_DATA2,
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PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
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PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
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PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
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mxc_iomux_set_pad(MX53_PIN_ATA_DATA3,
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PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
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PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
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PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
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break;
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default:
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printf("Warning: you configured more ESDHC controller"
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"(%d) as supported by the board(2)\n",
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CONFIG_SYS_FSL_ESDHC_NUM);
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return status;
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}
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status |= fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
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}
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return status;
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}
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#endif
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int board_early_init_f(void)
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{
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setup_iomux_uart();
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setup_iomux_fec();
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return 0;
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}
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int board_init(void)
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{
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/* address of boot parameters */
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gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
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return 0;
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}
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#ifdef CONFIG_CMD_BMODE
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static const struct boot_mode board_boot_modes[] = {
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/* 4 bit bus width */
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{"mmc0", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x12)},
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{"mmc1", MAKE_CFGVAL(0x40, 0x20, 0x08, 0x12)},
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{NULL, 0},
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};
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#endif
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int board_late_init(void)
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{
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setup_i2c(1);
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power_init();
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#ifdef CONFIG_CMD_BMODE
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add_board_boot_modes(board_boot_modes);
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#endif
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return 0;
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}
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int checkboard(void)
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{
|
|
puts("Board: MX53EVK\n");
|
|
|
|
return 0;
|
|
}
|