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https://github.com/brain-hackers/u-boot-brain
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3b97152b63
This patch uses the code in omap-common to support gpio modules 1-3 on am33xx based boards. It adds base address and register definitions, enables clocks to the modules, and enables building the common gpio code for CONFIG_AM33XX as well as CONFIG_OMAP Signed-off-by: Steve Sakoman <steve@sakoman.com>
129 lines
3.1 KiB
C
129 lines
3.1 KiB
C
/*
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* board.c
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*
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* Common board functions for AM33XX based boards
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*
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* Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <common.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/omap.h>
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#include <asm/arch/ddr_defs.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/gpio.h>
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#include <asm/arch/mmc_host_def.h>
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#include <asm/arch/common_def.h>
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#include <asm/io.h>
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#include <asm/omap_common.h>
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DECLARE_GLOBAL_DATA_PTR;
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struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
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struct gptimer *timer_base = (struct gptimer *)CONFIG_SYS_TIMERBASE;
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struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE;
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static const struct gpio_bank gpio_bank_am33xx[4] = {
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{ (void *)AM33XX_GPIO0_BASE, METHOD_GPIO_24XX },
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{ (void *)AM33XX_GPIO1_BASE, METHOD_GPIO_24XX },
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{ (void *)AM33XX_GPIO2_BASE, METHOD_GPIO_24XX },
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{ (void *)AM33XX_GPIO3_BASE, METHOD_GPIO_24XX },
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};
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const struct gpio_bank *const omap_gpio_bank = gpio_bank_am33xx;
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/* UART Defines */
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#ifdef CONFIG_SPL_BUILD
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#define UART_RESET (0x1 << 1)
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#define UART_CLK_RUNNING_MASK 0x1
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#define UART_SMART_IDLE_EN (0x1 << 0x3)
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#endif
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#ifdef CONFIG_SPL_BUILD
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/* Initialize timer */
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static void init_timer(void)
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{
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/* Reset the Timer */
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writel(0x2, (&timer_base->tscir));
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/* Wait until the reset is done */
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while (readl(&timer_base->tiocp_cfg) & 1)
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;
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/* Start the Timer */
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writel(0x1, (&timer_base->tclr));
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}
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#endif
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/*
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* early system init of muxing and clocks.
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*/
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void s_init(void)
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{
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/* WDT1 is already running when the bootloader gets control
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* Disable it to avoid "random" resets
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*/
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writel(0xAAAA, &wdtimer->wdtwspr);
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while (readl(&wdtimer->wdtwwps) != 0x0)
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;
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writel(0x5555, &wdtimer->wdtwspr);
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while (readl(&wdtimer->wdtwwps) != 0x0)
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;
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#ifdef CONFIG_SPL_BUILD
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/* Setup the PLLs and the clocks for the peripherals */
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pll_init();
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/* UART softreset */
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u32 regVal;
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enable_uart0_pin_mux();
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regVal = readl(&uart_base->uartsyscfg);
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regVal |= UART_RESET;
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writel(regVal, &uart_base->uartsyscfg);
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while ((readl(&uart_base->uartsyssts) &
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UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK)
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;
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/* Disable smart idle */
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regVal = readl(&uart_base->uartsyscfg);
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regVal |= UART_SMART_IDLE_EN;
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writel(regVal, &uart_base->uartsyscfg);
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/* Initialize the Timer */
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init_timer();
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preloader_console_init();
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config_ddr();
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#endif
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/* Enable MMC0 */
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enable_mmc0_pin_mux();
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}
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#if defined(CONFIG_OMAP_HSMMC) && !defined(CONFIG_SPL_BUILD)
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int board_mmc_init(bd_t *bis)
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{
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return omap_mmc_init(0, 0, 0);
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}
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#endif
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void setup_clocks_for_console(void)
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{
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/* Not yet implemented */
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return;
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}
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