mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-12 06:06:15 +09:00
e895a4b06f
This function can fail if the device tree runs out of space. Rather than silently booting with an incomplete device tree, allow the failure to be detected. Unfortunately this involves changing a lot of places in the code. I have not changed behvaiour to return an error where one is not currently returned, to avoid unexpected breakage. Eventually it would be nice to allow boards to register functions to be called to update the device tree. This would avoid all the many functions to do this. However it's not clear yet if this should be done using driver model or with a linker list. This work is left for later. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Anatolij Gustschin <agust@denx.de>
154 lines
3.1 KiB
C
154 lines
3.1 KiB
C
/*
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* Copyright 2013 Freescale Semiconductor, Inc.
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*
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* Authors: Roy Zang <tie-fei.zang@freescale.com>
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* Chunhe Lan <Chunhe.Lan@freescale.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <command.h>
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#include <pci.h>
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#include <asm/io.h>
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#include <asm/cache.h>
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#include <asm/processor.h>
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#include <asm/mmu.h>
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#include <asm/immap_85xx.h>
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#include <asm/fsl_pci.h>
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#include <fsl_ddr_sdram.h>
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#include <asm/fsl_portals.h>
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#include <libfdt.h>
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#include <fdt_support.h>
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#include <netdev.h>
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#include <malloc.h>
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#include <fm_eth.h>
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#include <fsl_mdio.h>
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#include <miiphy.h>
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#include <phy.h>
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#include <asm/fsl_dtsec.h>
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DECLARE_GLOBAL_DATA_PTR;
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int board_early_init_f(void)
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{
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fsl_lbc_t *lbc = LBC_BASE_ADDR;
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/* Set ABSWP to implement conversion of addresses in the LBC */
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setbits_be32(&lbc->lbcr, CONFIG_SYS_LBC_LBCR);
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return 0;
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}
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int checkboard(void)
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{
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printf("Board: P1023 RDB\n");
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return 0;
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}
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#ifdef CONFIG_PCI
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void pci_init_board(void)
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{
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fsl_pcie_init_board(0);
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}
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#endif
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int board_early_init_r(void)
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{
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const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
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int flash_esel = find_tlb_idx((void *)flashbase, 1);
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/*
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* Remap Boot flash + PROMJET region to caching-inhibited
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* so that flash can be erased properly.
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*/
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/* Flush d-cache and invalidate i-cache of any FLASH data */
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flush_dcache();
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invalidate_icache();
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if (flash_esel == -1) {
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/* very unlikely unless something is messed up */
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puts("Error: Could not find TLB for FLASH BASE\n");
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flash_esel = 2; /* give our best effort to continue */
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} else {
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/* invalidate existing TLB entry for flash + promjet */
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disable_tlb(flash_esel);
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}
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set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
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MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
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0, flash_esel, BOOKE_PAGESZ_256M, 1);
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setup_portals();
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return 0;
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}
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unsigned long get_board_sys_clk(ulong dummy)
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{
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return gd->bus_clk;
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}
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unsigned long get_board_ddr_clk(ulong dummy)
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{
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return gd->mem_clk;
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}
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int board_eth_init(bd_t *bis)
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{
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ccsr_gur_t *gur = (ccsr_gur_t *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
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struct fsl_pq_mdio_info dtsec_mdio_info;
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/*
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* Need to set dTSEC 1 pin multiplexing to TSEC. The default setting
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* is not correct.
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*/
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setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_TSEC1_1);
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dtsec_mdio_info.regs =
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(struct tsec_mii_mng *)CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR;
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dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
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/* Register the 1G MDIO bus */
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fsl_pq_mdio_init(bis, &dtsec_mdio_info);
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fm_info_set_phy_address(FM1_DTSEC1, CONFIG_SYS_FM1_DTSEC1_PHY_ADDR);
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fm_info_set_phy_address(FM1_DTSEC2, CONFIG_SYS_FM1_DTSEC2_PHY_ADDR);
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fm_info_set_mdio(FM1_DTSEC1,
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miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME));
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fm_info_set_mdio(FM1_DTSEC2,
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miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME));
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#ifdef CONFIG_FMAN_ENET
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cpu_eth_init(bis);
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#endif
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return pci_eth_init(bis);
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}
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#if defined(CONFIG_OF_BOARD_SETUP)
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int ft_board_setup(void *blob, bd_t *bd)
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{
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phys_addr_t base;
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phys_size_t size;
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ft_cpu_setup(blob, bd);
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base = getenv_bootm_low();
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size = getenv_bootm_size();
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fdt_fixup_memory(blob, (u64)base, (u64)size);
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#ifdef CONFIG_HAS_FSL_DR_USB
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fdt_fixup_dr_usb(blob, bd);
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#endif
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fdt_fixup_fman_ethernet(blob);
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return 0;
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}
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#endif
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