Bin Meng 3b621ccabd x86: Test mtrr support flag before accessing mtrr msr ... On some x86 processors (like Intel Quark) the MTRR registers are not supported. This is reflected by the CPUID (EAX 01H) result EDX[12]. Accessing the MTRR registers on such processors will cause #GP so we must test the support flag before accessing MTRR MSRs. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>		2015-01-23 17:24:55 -07:00
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coreboot	x86: coreboot: Configure pci memory regions	2015-01-13 07:25:05 -08:00
ivybridge	x86: ivybridge: Update microcode early in boot	2015-01-13 07:25:02 -08:00
queensbay	x86: fsp: Drop get_hob_type() and get_hob_length()	2015-01-13 07:25:02 -08:00
call64.S	x86: Add support for starting 64-bit kernel	2014-10-28 20:43:47 -06:00
config.mk	x86: Factor out common values in the link script	2014-11-25 06:33:59 -07:00
cpu.c	x86: Save mtrr support flag in global data	2015-01-23 17:24:55 -07:00
interrupts.c	x86: Drop old CONFIG_INTEL_CORE_ARCH code	2014-11-25 06:34:03 -07:00
lapic.c	x86: Add LAPIC setup code	2014-11-25 06:34:11 -07:00
Makefile	x86: Add support for MTRRs	2015-01-13 07:25:00 -08:00
mtrr.c	x86: Test mtrr support flag before accessing mtrr msr	2015-01-23 17:24:55 -07:00
pci.c	pci: Make pci apis usable before relocation	2015-01-12 17:03:41 -08:00
resetvec.S	Add GPL-2.0+ SPDX-License-Identifier to source files	2013-07-24 09:44:38 -04:00
start16.S	x86: Save the BIST value on reset	2014-11-21 07:24:10 +01:00
start.S	x86: Disable CAR before relocation on platforms that need it	2015-01-13 07:25:01 -08:00
turbo.c	x86: Add Intel speedstep and turbo mode code	2014-11-25 06:34:02 -07:00
u-boot.lds	x86: Factor out common values in the link script	2014-11-25 06:33:59 -07:00