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https://github.com/brain-hackers/u-boot-brain
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3eb90bad65
According to the PPC reference implementation the udelay() function is responsible for resetting the watchdog timer as frequently as needed. Most other architectures do not meet that requirement, so long-running operations might result in a watchdog reset. This patch adds a generic udelay() function which takes care of resetting the watchdog before calling an architecture-specific __udelay(). Signed-off-by: Ingo van Lil <inguin@gmx.de>
135 lines
3.6 KiB
C
135 lines
3.6 KiB
C
/*
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* Copyright (C) Freescale Semiconductor, Inc. 2006-2007
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*
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* Authors: Nick.Spence@freescale.com
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* Wilson.Lo@freescale.com
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* scottwood@freescale.com
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <mpc83xx.h>
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#include <spd_sdram.h>
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#include <asm/bitops.h>
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#include <asm/io.h>
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#include <asm/processor.h>
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DECLARE_GLOBAL_DATA_PTR;
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#ifndef CONFIG_SYS_8313ERDB_BROKEN_PMC
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static void resume_from_sleep(void)
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{
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u32 magic = *(u32 *)0;
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typedef void (*func_t)(void);
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func_t resume = *(func_t *)4;
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if (magic == 0xf5153ae5)
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resume();
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gd->flags &= ~GD_FLG_SILENT;
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puts("\nResume from sleep failed: bad magic word\n");
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}
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#endif
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/* Fixed sdram init -- doesn't use serial presence detect.
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*
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* This is useful for faster booting in configs where the RAM is unlikely
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* to be changed, or for things like NAND booting where space is tight.
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*/
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static long fixed_sdram(void)
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{
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u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
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#ifndef CONFIG_SYS_RAMBOOT
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volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
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u32 msize_log2 = __ilog2(msize);
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im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
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im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1);
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im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE;
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/*
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* Erratum DDR3 requires a 50ms delay after clearing DDRCDR[DDR_cfg],
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* or the DDR2 controller may fail to initialize correctly.
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*/
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__udelay(50000);
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im->ddr.csbnds[0].csbnds = (msize - 1) >> 24;
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im->ddr.cs_config[0] = CONFIG_SYS_DDR_CONFIG;
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/* Currently we use only one CS, so disable the other bank. */
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im->ddr.cs_config[1] = 0;
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im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL;
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im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
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im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
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im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
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im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
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#ifndef CONFIG_SYS_8313ERDB_BROKEN_PMC
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if (im->pmc.pmccr1 & PMCCR1_POWER_OFF)
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im->ddr.sdram_cfg = CONFIG_SYS_SDRAM_CFG | SDRAM_CFG_BI;
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else
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#endif
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im->ddr.sdram_cfg = CONFIG_SYS_SDRAM_CFG;
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im->ddr.sdram_cfg2 = CONFIG_SYS_SDRAM_CFG2;
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im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
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im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE_2;
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im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
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sync();
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/* enable DDR controller */
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im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
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#endif
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return msize;
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}
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phys_size_t initdram(int board_type)
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{
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volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
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volatile fsl_lbus_t *lbc = &im->lbus;
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u32 msize;
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if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
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return -1;
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/* DDR SDRAM - Main SODIMM */
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msize = fixed_sdram();
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/* Local Bus setup lbcr and mrtpr */
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lbc->lbcr = CONFIG_SYS_LBC_LBCR;
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lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
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sync();
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#ifndef CONFIG_SYS_8313ERDB_BROKEN_PMC
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if (im->pmc.pmccr1 & PMCCR1_POWER_OFF)
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resume_from_sleep();
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#endif
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/* return total bus SDRAM size(bytes) -- DDR */
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return msize;
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}
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