mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-22 19:09:43 +09:00
5fa030b9f0
We should not init the console this early since it precludes using driver model for the UART, since it is not set up at the start of board_init_f(). See the README for more information. The debug UART does not have this restriction. If we want to do early init with the console on it can be done in spl_board_init(). Move the preloader_console_init() call from board_init_f() to board_init_r(). Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Masahiro Yamada <yamada.masahiro@socionext.com> Tested-by: Michal Simek <michal.simek@xilinx.com>
91 lines
1.4 KiB
C
91 lines
1.4 KiB
C
/*
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* (C) Copyright 2014 Xilinx, Inc. Michal Simek
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <spl.h>
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#include <asm/io.h>
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#include <asm/arch/hardware.h>
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#include <asm/spl.h>
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#include <asm/arch/sys_proto.h>
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DECLARE_GLOBAL_DATA_PTR;
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void board_init_f(ulong dummy)
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{
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ps7_init();
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/* Clear the BSS. */
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memset(__bss_start, 0, __bss_end - __bss_start);
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arch_cpu_init();
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board_init_r(NULL, 0);
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}
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#ifdef CONFIG_SPL_BOARD_INIT
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void spl_board_init(void)
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{
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preloader_console_init();
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board_init();
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}
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#endif
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u32 spl_boot_device(void)
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{
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u32 mode;
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switch ((zynq_slcr_get_boot_mode()) & ZYNQ_BM_MASK) {
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#ifdef CONFIG_SPL_SPI_SUPPORT
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case ZYNQ_BM_QSPI:
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puts("qspi boot\n");
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mode = BOOT_DEVICE_SPI;
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break;
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#endif
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case ZYNQ_BM_NAND:
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mode = BOOT_DEVICE_NAND;
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break;
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case ZYNQ_BM_NOR:
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mode = BOOT_DEVICE_NOR;
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break;
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#ifdef CONFIG_SPL_MMC_SUPPORT
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case ZYNQ_BM_SD:
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puts("mmc boot\n");
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mode = BOOT_DEVICE_MMC1;
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break;
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#endif
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case ZYNQ_BM_JTAG:
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mode = BOOT_DEVICE_RAM;
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break;
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default:
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puts("Unsupported boot mode selected\n");
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hang();
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}
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return mode;
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}
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#ifdef CONFIG_SPL_MMC_SUPPORT
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u32 spl_boot_mode(void)
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{
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return MMCSD_MODE_FS;
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}
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#endif
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#ifdef CONFIG_SPL_OS_BOOT
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int spl_start_uboot(void)
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{
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/* boot linux */
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return 0;
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}
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#endif
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__weak void ps7_init(void)
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{
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/*
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* This function is overridden by the one in
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* board/xilinx/zynq/(platform)/ps7_init_gpl.c, if it exists.
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*/
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}
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