mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
132 lines
3.9 KiB
C
132 lines
3.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2012-2020 ASPEED Technology Inc.
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* Copyright 2016 IBM Corporation
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* Copyright 2017 Google, Inc.
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*/
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#ifndef __AST_I2C_H_
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#define __AST_I2C_H_
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struct ast_i2c_regs {
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u32 fcr;
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u32 cactcr1;
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u32 cactcr2;
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u32 icr;
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u32 isr;
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u32 csr;
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u32 sdar;
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u32 pbcr;
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u32 trbbr;
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#ifdef CONFIG_ASPEED_AST2500
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u32 dma_mbar;
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u32 dma_tlr;
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#endif
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};
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/* Device Register Definition */
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/* 0x00 : I2CD Function Control Register */
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#define I2CD_BUFF_SEL_MASK (0x7 << 20)
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#define I2CD_BUFF_SEL(x) (x << 20)
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#define I2CD_M_SDA_LOCK_EN (0x1 << 16)
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#define I2CD_MULTI_MASTER_DIS (0x1 << 15)
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#define I2CD_M_SCL_DRIVE_EN (0x1 << 14)
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#define I2CD_MSB_STS (0x1 << 9)
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#define I2CD_SDA_DRIVE_1T_EN (0x1 << 8)
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#define I2CD_M_SDA_DRIVE_1T_EN (0x1 << 7)
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#define I2CD_M_HIGH_SPEED_EN (0x1 << 6)
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#define I2CD_DEF_ADDR_EN (0x1 << 5)
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#define I2CD_DEF_ALERT_EN (0x1 << 4)
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#define I2CD_DEF_ARP_EN (0x1 << 3)
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#define I2CD_DEF_GCALL_EN (0x1 << 2)
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#define I2CD_SLAVE_EN (0x1 << 1)
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#define I2CD_MASTER_EN (0x1)
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/* 0x04 : I2CD Clock and AC Timing Control Register #1 */
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/* Base register value. These bits are always set by the driver. */
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#define I2CD_CACTC_BASE 0xfff00300
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#define I2CD_TCKHIGH_SHIFT 16
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#define I2CD_TCKLOW_SHIFT 12
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#define I2CD_THDDAT_SHIFT 10
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#define I2CD_TO_DIV_SHIFT 8
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#define I2CD_BASE_DIV_SHIFT 0
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/* 0x08 : I2CD Clock and AC Timing Control Register #2 */
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#define I2CD_tTIMEOUT 1
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#define I2CD_NO_TIMEOUT_CTRL 0
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/* 0x0c : I2CD Interrupt Control Register &
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* 0x10 : I2CD Interrupt Status Register
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*
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* These share bit definitions, so use the same values for the enable &
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* status bits.
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*/
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#define I2CD_INTR_SDA_DL_TIMEOUT (0x1 << 14)
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#define I2CD_INTR_BUS_RECOVER_DONE (0x1 << 13)
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#define I2CD_INTR_SMBUS_ALERT (0x1 << 12)
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#define I2CD_INTR_SMBUS_ARP_ADDR (0x1 << 11)
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#define I2CD_INTR_SMBUS_DEV_ALERT_ADDR (0x1 << 10)
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#define I2CD_INTR_SMBUS_DEF_ADDR (0x1 << 9)
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#define I2CD_INTR_GCALL_ADDR (0x1 << 8)
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#define I2CD_INTR_SLAVE_MATCH (0x1 << 7)
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#define I2CD_INTR_SCL_TIMEOUT (0x1 << 6)
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#define I2CD_INTR_ABNORMAL (0x1 << 5)
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#define I2CD_INTR_NORMAL_STOP (0x1 << 4)
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#define I2CD_INTR_ARBIT_LOSS (0x1 << 3)
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#define I2CD_INTR_RX_DONE (0x1 << 2)
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#define I2CD_INTR_TX_NAK (0x1 << 1)
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#define I2CD_INTR_TX_ACK (0x1 << 0)
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/* 0x14 : I2CD Command/Status Register */
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#define I2CD_SDA_OE (0x1 << 28)
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#define I2CD_SDA_O (0x1 << 27)
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#define I2CD_SCL_OE (0x1 << 26)
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#define I2CD_SCL_O (0x1 << 25)
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#define I2CD_TX_TIMING (0x1 << 24)
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#define I2CD_TX_STATUS (0x1 << 23)
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/* Tx State Machine */
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#define I2CD_IDLE 0x0
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#define I2CD_MACTIVE 0x8
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#define I2CD_MSTART 0x9
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#define I2CD_MSTARTR 0xa
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#define I2CD_MSTOP 0xb
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#define I2CD_MTXD 0xc
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#define I2CD_MRXACK 0xd
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#define I2CD_MRXD 0xe
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#define I2CD_MTXACK 0xf
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#define I2CD_SWAIT 0x1
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#define I2CD_SRXD 0x4
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#define I2CD_STXACK 0x5
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#define I2CD_STXD 0x6
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#define I2CD_SRXACK 0x7
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#define I2CD_RECOVER 0x3
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#define I2CD_SCL_LINE_STS (0x1 << 18)
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#define I2CD_SDA_LINE_STS (0x1 << 17)
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#define I2CD_BUS_BUSY_STS (0x1 << 16)
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#define I2CD_SDA_OE_OUT_DIR (0x1 << 15)
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#define I2CD_SDA_O_OUT_DIR (0x1 << 14)
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#define I2CD_SCL_OE_OUT_DIR (0x1 << 13)
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#define I2CD_SCL_O_OUT_DIR (0x1 << 12)
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#define I2CD_BUS_RECOVER_CMD (0x1 << 11)
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#define I2CD_S_ALT_EN (0x1 << 10)
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#define I2CD_RX_DMA_ENABLE (0x1 << 9)
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#define I2CD_TX_DMA_ENABLE (0x1 << 8)
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/* Command Bit */
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#define I2CD_RX_BUFF_ENABLE (0x1 << 7)
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#define I2CD_TX_BUFF_ENABLE (0x1 << 6)
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#define I2CD_M_STOP_CMD (0x1 << 5)
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#define I2CD_M_S_RX_CMD_LAST (0x1 << 4)
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#define I2CD_M_RX_CMD (0x1 << 3)
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#define I2CD_S_TX_CMD (0x1 << 2)
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#define I2CD_M_TX_CMD (0x1 << 1)
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#define I2CD_M_START_CMD 0x1
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#define I2CD_RX_DATA_SHIFT 8
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#define I2CD_RX_DATA_MASK (0xff << I2CD_RX_DATA_SHIFT)
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#define I2C_HIGHSPEED_RATE 400000
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#endif /* __AST_I2C_H_ */
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