mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-06 19:26:16 +09:00
ae485b540f
This commit adds Actions Semi OWL family base clock and S900 SoC specific clock support. For S900 peripheral clock support, only UART clock has been added for now. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Simon Glass <sjg@chromium.org>
139 lines
3.0 KiB
C
139 lines
3.0 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Actions Semi S900 clock driver
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*
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* Copyright (C) 2015 Actions Semi Co., Ltd.
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* Copyright (C) 2018 Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
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*/
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#include <common.h>
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#include <dm.h>
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#include <asm/arch-owl/clk_s900.h>
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#include <asm/arch-owl/regs_s900.h>
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#include <asm/io.h>
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#include <dt-bindings/clock/s900_cmu.h>
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void owl_clk_init(struct owl_clk_priv *priv)
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{
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u32 bus_clk = 0, core_pll, dev_pll;
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/* Enable ASSIST_PLL */
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setbits_le32(priv->base + CMU_ASSISTPLL, BIT(0));
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udelay(PLL_STABILITY_WAIT_US);
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/* Source HOSC to DEV_CLK */
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clrbits_le32(priv->base + CMU_DEVPLL, CMU_DEVPLL_CLK);
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/* Configure BUS_CLK */
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bus_clk |= (CMU_PDBGDIV_DIV | CMU_PERDIV_DIV | CMU_NOCDIV_DIV |
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CMU_DMMCLK_SRC | CMU_APBCLK_DIV | CMU_AHBCLK_DIV |
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CMU_NOCCLK_SRC | CMU_CORECLK_HOSC);
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writel(bus_clk, priv->base + CMU_BUSCLK);
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udelay(PLL_STABILITY_WAIT_US);
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/* Configure CORE_PLL */
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core_pll = readl(priv->base + CMU_COREPLL);
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core_pll |= (CMU_COREPLL_EN | CMU_COREPLL_HOSC_EN | CMU_COREPLL_OUT);
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writel(core_pll, priv->base + CMU_COREPLL);
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udelay(PLL_STABILITY_WAIT_US);
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/* Configure DEV_PLL */
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dev_pll = readl(priv->base + CMU_DEVPLL);
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dev_pll |= (CMU_DEVPLL_EN | CMU_DEVPLL_OUT);
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writel(dev_pll, priv->base + CMU_DEVPLL);
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udelay(PLL_STABILITY_WAIT_US);
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/* Source CORE_PLL for CORE_CLK */
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clrsetbits_le32(priv->base + CMU_BUSCLK, CMU_CORECLK_MASK,
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CMU_CORECLK_CPLL);
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/* Source DEV_PLL for DEV_CLK */
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setbits_le32(priv->base + CMU_DEVPLL, CMU_DEVPLL_CLK);
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udelay(PLL_STABILITY_WAIT_US);
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}
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void owl_uart_clk_enable(struct owl_clk_priv *priv)
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{
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/* Source HOSC for UART5 interface */
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clrbits_le32(priv->base + CMU_UART5CLK, CMU_UARTCLK_SRC_DEVPLL);
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/* Enable UART5 interface clock */
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setbits_le32(priv->base + CMU_DEVCLKEN1, CMU_DEVCLKEN1_UART5);
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}
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void owl_uart_clk_disable(struct owl_clk_priv *priv)
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{
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/* Disable UART5 interface clock */
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clrbits_le32(priv->base + CMU_DEVCLKEN1, CMU_DEVCLKEN1_UART5);
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}
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int owl_clk_enable(struct clk *clk)
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{
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struct owl_clk_priv *priv = dev_get_priv(clk->dev);
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switch (clk->id) {
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case CLOCK_UART5:
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owl_uart_clk_enable(priv);
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break;
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default:
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return 0;
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}
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return 0;
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}
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int owl_clk_disable(struct clk *clk)
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{
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struct owl_clk_priv *priv = dev_get_priv(clk->dev);
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switch (clk->id) {
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case CLOCK_UART5:
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owl_uart_clk_disable(priv);
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break;
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default:
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return 0;
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}
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return 0;
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}
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static int owl_clk_probe(struct udevice *dev)
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{
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struct owl_clk_priv *priv = dev_get_priv(dev);
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priv->base = dev_read_addr(dev);
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if (priv->base == FDT_ADDR_T_NONE)
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return -EINVAL;
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/* setup necessary clocks */
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owl_clk_init(priv);
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return 0;
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}
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static struct clk_ops owl_clk_ops = {
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.enable = owl_clk_enable,
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.disable = owl_clk_disable,
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};
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static const struct udevice_id owl_clk_ids[] = {
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{ .compatible = "actions,s900-cmu" },
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{ }
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};
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U_BOOT_DRIVER(clk_owl) = {
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.name = "clk_s900",
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.id = UCLASS_CLK,
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.of_match = owl_clk_ids,
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.ops = &owl_clk_ops,
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.priv_auto_alloc_size = sizeof(struct owl_clk_priv),
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.probe = owl_clk_probe,
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.flags = DM_FLAG_PRE_RELOC,
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};
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