mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-09-20 11:40:25 +09:00
3acb553439
TPS SET0/SET1 register is selected by a GPIO pin on OMAP4460 platforms.
Currently we control this pin with a mux configuration as part of
boot sequence.
Current configuration results in the following voltage waveform:
|---------------| (SET1 default 1.4V)
| --------(programmed voltage)
| <- (This switch happens on mux7,pullup)
vdd_mpu(TPS) -----/ (OPP boot voltage)
--------- (programmed voltage)
vdd_core(TWL6030) -----------------------/ (OPP boot voltage)
Problem 1) |<----- Tx ------>|
timing violation for a duration Tx close to few milliseconds.
Problem 2) voltage of MPU goes beyond spec for even the highest of MPU OPP.
By using GPIO as recommended as standard procedure by TI, the sequence
changes to:
-------- (programmed voltage)
vdd_mpu(TPS) ------------/ (Opp boot voltage)
--------- (programmed voltage)
vdd_core(TWL6030) -------------/ (OPP boot voltage)
NOTE: This does not attempt to address OMAP5 - Aneesh please confirm
Reported-by: Isabelle Gros <i-gros@ti.com>
Reported-by: Jerome Angeloni <j-angeloni@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
506 lines
15 KiB
C
506 lines
15 KiB
C
/*
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*
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* Clock initialization for OMAP4
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*
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* (C) Copyright 2010
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* Texas Instruments, <www.ti.com>
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*
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* Aneesh V <aneesh@ti.com>
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*
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* Based on previous work by:
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* Santosh Shilimkar <santosh.shilimkar@ti.com>
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* Rajendra Nayak <rnayak@ti.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/omap_common.h>
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#include <asm/gpio.h>
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#include <asm/arch/clocks.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/utils.h>
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#include <asm/omap_gpio.h>
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#ifndef CONFIG_SPL_BUILD
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/*
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* printing to console doesn't work unless
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* this code is executed from SPL
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*/
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#define printf(fmt, args...)
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#define puts(s)
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#endif
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#define abs(x) (((x) < 0) ? ((x)*-1) : (x))
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struct omap4_prcm_regs *const prcm = (struct omap4_prcm_regs *)0x4A004100;
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const u32 sys_clk_array[8] = {
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12000000, /* 12 MHz */
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13000000, /* 13 MHz */
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16800000, /* 16.8 MHz */
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19200000, /* 19.2 MHz */
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26000000, /* 26 MHz */
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27000000, /* 27 MHz */
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38400000, /* 38.4 MHz */
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};
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/*
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* The M & N values in the following tables are created using the
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* following tool:
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* tools/omap/clocks_get_m_n.c
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* Please use this tool for creating the table for any new frequency.
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*/
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/* dpll locked at 1400 MHz MPU clk at 700 MHz(OPP100) - DCC OFF */
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static const struct dpll_params mpu_dpll_params_1400mhz[NUM_SYS_CLKS] = {
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{175, 2, 1, -1, -1, -1, -1, -1}, /* 12 MHz */
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{700, 12, 1, -1, -1, -1, -1, -1}, /* 13 MHz */
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{125, 2, 1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
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{401, 10, 1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
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{350, 12, 1, -1, -1, -1, -1, -1}, /* 26 MHz */
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{700, 26, 1, -1, -1, -1, -1, -1}, /* 27 MHz */
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{638, 34, 1, -1, -1, -1, -1, -1} /* 38.4 MHz */
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};
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/* dpll locked at 1584 MHz - MPU clk at 792 MHz(OPP Turbo 4430) */
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static const struct dpll_params mpu_dpll_params_1600mhz[NUM_SYS_CLKS] = {
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{200, 2, 1, -1, -1, -1, -1, -1}, /* 12 MHz */
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{800, 12, 1, -1, -1, -1, -1, -1}, /* 13 MHz */
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{619, 12, 1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
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{125, 2, 1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
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{400, 12, 1, -1, -1, -1, -1, -1}, /* 26 MHz */
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{800, 26, 1, -1, -1, -1, -1, -1}, /* 27 MHz */
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{125, 5, 1, -1, -1, -1, -1, -1} /* 38.4 MHz */
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};
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/* dpll locked at 1200 MHz - MPU clk at 600 MHz */
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static const struct dpll_params mpu_dpll_params_1200mhz[NUM_SYS_CLKS] = {
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{50, 0, 1, -1, -1, -1, -1, -1}, /* 12 MHz */
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{600, 12, 1, -1, -1, -1, -1, -1}, /* 13 MHz */
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{250, 6, 1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
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{125, 3, 1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
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{300, 12, 1, -1, -1, -1, -1, -1}, /* 26 MHz */
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{200, 8, 1, -1, -1, -1, -1, -1}, /* 27 MHz */
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{125, 7, 1, -1, -1, -1, -1, -1} /* 38.4 MHz */
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};
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static const struct dpll_params core_dpll_params_1600mhz[NUM_SYS_CLKS] = {
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{200, 2, 1, 5, 8, 4, 6, 5}, /* 12 MHz */
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{800, 12, 1, 5, 8, 4, 6, 5}, /* 13 MHz */
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{619, 12, 1, 5, 8, 4, 6, 5}, /* 16.8 MHz */
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{125, 2, 1, 5, 8, 4, 6, 5}, /* 19.2 MHz */
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{400, 12, 1, 5, 8, 4, 6, 5}, /* 26 MHz */
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{800, 26, 1, 5, 8, 4, 6, 5}, /* 27 MHz */
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{125, 5, 1, 5, 8, 4, 6, 5} /* 38.4 MHz */
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};
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static const struct dpll_params core_dpll_params_es1_1524mhz[NUM_SYS_CLKS] = {
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{127, 1, 1, 5, 8, 4, 6, 5}, /* 12 MHz */
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{762, 12, 1, 5, 8, 4, 6, 5}, /* 13 MHz */
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{635, 13, 1, 5, 8, 4, 6, 5}, /* 16.8 MHz */
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{635, 15, 1, 5, 8, 4, 6, 5}, /* 19.2 MHz */
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{381, 12, 1, 5, 8, 4, 6, 5}, /* 26 MHz */
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{254, 8, 1, 5, 8, 4, 6, 5}, /* 27 MHz */
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{496, 24, 1, 5, 8, 4, 6, 5} /* 38.4 MHz */
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};
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static const struct dpll_params
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core_dpll_params_es2_1600mhz_ddr200mhz[NUM_SYS_CLKS] = {
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{200, 2, 2, 5, 8, 4, 6, 5}, /* 12 MHz */
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{800, 12, 2, 5, 8, 4, 6, 5}, /* 13 MHz */
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{619, 12, 2, 5, 8, 4, 6, 5}, /* 16.8 MHz */
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{125, 2, 2, 5, 8, 4, 6, 5}, /* 19.2 MHz */
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{400, 12, 2, 5, 8, 4, 6, 5}, /* 26 MHz */
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{800, 26, 2, 5, 8, 4, 6, 5}, /* 27 MHz */
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{125, 5, 2, 5, 8, 4, 6, 5} /* 38.4 MHz */
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};
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static const struct dpll_params per_dpll_params_1536mhz[NUM_SYS_CLKS] = {
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{64, 0, 8, 6, 12, 9, 4, 5}, /* 12 MHz */
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{768, 12, 8, 6, 12, 9, 4, 5}, /* 13 MHz */
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{320, 6, 8, 6, 12, 9, 4, 5}, /* 16.8 MHz */
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{40, 0, 8, 6, 12, 9, 4, 5}, /* 19.2 MHz */
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{384, 12, 8, 6, 12, 9, 4, 5}, /* 26 MHz */
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{256, 8, 8, 6, 12, 9, 4, 5}, /* 27 MHz */
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{20, 0, 8, 6, 12, 9, 4, 5} /* 38.4 MHz */
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};
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static const struct dpll_params iva_dpll_params_1862mhz[NUM_SYS_CLKS] = {
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{931, 11, -1, -1, 4, 7, -1, -1}, /* 12 MHz */
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{931, 12, -1, -1, 4, 7, -1, -1}, /* 13 MHz */
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{665, 11, -1, -1, 4, 7, -1, -1}, /* 16.8 MHz */
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{727, 14, -1, -1, 4, 7, -1, -1}, /* 19.2 MHz */
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{931, 25, -1, -1, 4, 7, -1, -1}, /* 26 MHz */
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{931, 26, -1, -1, 4, 7, -1, -1}, /* 27 MHz */
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{412, 16, -1, -1, 4, 7, -1, -1} /* 38.4 MHz */
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};
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/* ABE M & N values with sys_clk as source */
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static const struct dpll_params
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abe_dpll_params_sysclk_196608khz[NUM_SYS_CLKS] = {
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{49, 5, 1, 1, -1, -1, -1, -1}, /* 12 MHz */
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{68, 8, 1, 1, -1, -1, -1, -1}, /* 13 MHz */
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{35, 5, 1, 1, -1, -1, -1, -1}, /* 16.8 MHz */
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{46, 8, 1, 1, -1, -1, -1, -1}, /* 19.2 MHz */
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{34, 8, 1, 1, -1, -1, -1, -1}, /* 26 MHz */
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{29, 7, 1, 1, -1, -1, -1, -1}, /* 27 MHz */
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{64, 24, 1, 1, -1, -1, -1, -1} /* 38.4 MHz */
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};
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/* ABE M & N values with 32K clock as source */
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static const struct dpll_params abe_dpll_params_32k_196608khz = {
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750, 0, 1, 1, -1, -1, -1, -1
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};
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static const struct dpll_params usb_dpll_params_1920mhz[NUM_SYS_CLKS] = {
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{80, 0, 2, -1, -1, -1, -1, -1}, /* 12 MHz */
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{960, 12, 2, -1, -1, -1, -1, -1}, /* 13 MHz */
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{400, 6, 2, -1, -1, -1, -1, -1}, /* 16.8 MHz */
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{50, 0, 2, -1, -1, -1, -1, -1}, /* 19.2 MHz */
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{480, 12, 2, -1, -1, -1, -1, -1}, /* 26 MHz */
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{320, 8, 2, -1, -1, -1, -1, -1}, /* 27 MHz */
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{25, 0, 2, -1, -1, -1, -1, -1} /* 38.4 MHz */
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};
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void setup_post_dividers(u32 *const base, const struct dpll_params *params)
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{
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struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
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/* Setup post-dividers */
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if (params->m2 >= 0)
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writel(params->m2, &dpll_regs->cm_div_m2_dpll);
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if (params->m3 >= 0)
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writel(params->m3, &dpll_regs->cm_div_m3_dpll);
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if (params->m4 >= 0)
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writel(params->m4, &dpll_regs->cm_div_m4_dpll);
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if (params->m5 >= 0)
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writel(params->m5, &dpll_regs->cm_div_m5_dpll);
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if (params->m6 >= 0)
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writel(params->m6, &dpll_regs->cm_div_m6_dpll);
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if (params->m7 >= 0)
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writel(params->m7, &dpll_regs->cm_div_m7_dpll);
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}
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/*
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* Lock MPU dpll
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*
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* Resulting MPU frequencies:
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* 4430 ES1.0 : 600 MHz
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* 4430 ES2.x : 792 MHz (OPP Turbo)
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* 4460 : 920 MHz (OPP Turbo) - DCC disabled
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*/
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const struct dpll_params *get_mpu_dpll_params(void)
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{
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u32 omap_rev, sysclk_ind;
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omap_rev = omap_revision();
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sysclk_ind = get_sys_clk_index();
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if (omap_rev == OMAP4430_ES1_0)
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return &mpu_dpll_params_1200mhz[sysclk_ind];
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else if (omap_rev < OMAP4460_ES1_0)
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return &mpu_dpll_params_1600mhz[sysclk_ind];
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else
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return &mpu_dpll_params_1400mhz[sysclk_ind];
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}
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const struct dpll_params *get_core_dpll_params(void)
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{
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u32 sysclk_ind = get_sys_clk_index();
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switch (omap_revision()) {
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case OMAP4430_ES1_0:
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return &core_dpll_params_es1_1524mhz[sysclk_ind];
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case OMAP4430_ES2_0:
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case OMAP4430_SILICON_ID_INVALID:
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/* safest */
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return &core_dpll_params_es2_1600mhz_ddr200mhz[sysclk_ind];
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default:
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return &core_dpll_params_1600mhz[sysclk_ind];
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}
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}
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const struct dpll_params *get_per_dpll_params(void)
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{
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u32 sysclk_ind = get_sys_clk_index();
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return &per_dpll_params_1536mhz[sysclk_ind];
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}
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const struct dpll_params *get_iva_dpll_params(void)
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{
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u32 sysclk_ind = get_sys_clk_index();
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return &iva_dpll_params_1862mhz[sysclk_ind];
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}
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const struct dpll_params *get_usb_dpll_params(void)
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{
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u32 sysclk_ind = get_sys_clk_index();
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return &usb_dpll_params_1920mhz[sysclk_ind];
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}
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const struct dpll_params *get_abe_dpll_params(void)
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{
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#ifdef CONFIG_SYS_OMAP_ABE_SYSCK
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u32 sysclk_ind = get_sys_clk_index();
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return &abe_dpll_params_sysclk_196608khz[sysclk_ind];
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#else
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return &abe_dpll_params_32k_196608khz;
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#endif
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}
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/*
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* Setup the voltages for vdd_mpu, vdd_core, and vdd_iva
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* We set the maximum voltages allowed here because Smart-Reflex is not
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* enabled in bootloader. Voltage initialization in the kernel will set
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* these to the nominal values after enabling Smart-Reflex
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*/
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void scale_vcores(void)
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{
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u32 volt, omap_rev;
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omap_vc_init(PRM_VC_I2C_CHANNEL_FREQ_KHZ);
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omap_rev = omap_revision();
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/* TPS - supplies vdd_mpu on 4460 */
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if (omap_rev >= OMAP4460_ES1_0) {
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volt = 1203;
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do_scale_tps62361(TPS62361_VSEL0_GPIO,
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TPS62361_REG_ADDR_SET1, volt);
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}
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/*
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* VCORE 1
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*
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* 4430 : supplies vdd_mpu
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* Setting a high voltage for Nitro mode as smart reflex is not enabled.
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* We use the maximum possible value in the AVS range because the next
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* higher voltage in the discrete range (code >= 0b111010) is way too
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* high
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*
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* 4460 : supplies vdd_core
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*/
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if (omap_rev < OMAP4460_ES1_0) {
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volt = 1325;
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do_scale_vcore(SMPS_REG_ADDR_VCORE1, volt);
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} else {
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volt = 1200;
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do_scale_vcore(SMPS_REG_ADDR_VCORE1, volt);
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}
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/* VCORE 2 - supplies vdd_iva */
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volt = 1200;
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do_scale_vcore(SMPS_REG_ADDR_VCORE2, volt);
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/*
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* VCORE 3
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* 4430 : supplies vdd_core
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* 4460 : not connected
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*/
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if (omap_rev < OMAP4460_ES1_0) {
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volt = 1200;
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do_scale_vcore(SMPS_REG_ADDR_VCORE3, volt);
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}
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}
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/*
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* Enable essential clock domains, modules and
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* do some additional special settings needed
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*/
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void enable_basic_clocks(void)
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{
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u32 *const clk_domains_essential[] = {
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&prcm->cm_l4per_clkstctrl,
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&prcm->cm_l3init_clkstctrl,
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&prcm->cm_memif_clkstctrl,
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&prcm->cm_l4cfg_clkstctrl,
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0
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};
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u32 *const clk_modules_hw_auto_essential[] = {
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&prcm->cm_memif_emif_1_clkctrl,
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&prcm->cm_memif_emif_2_clkctrl,
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&prcm->cm_l4cfg_l4_cfg_clkctrl,
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&prcm->cm_wkup_gpio1_clkctrl,
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&prcm->cm_l4per_gpio2_clkctrl,
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&prcm->cm_l4per_gpio3_clkctrl,
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&prcm->cm_l4per_gpio4_clkctrl,
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&prcm->cm_l4per_gpio5_clkctrl,
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&prcm->cm_l4per_gpio6_clkctrl,
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&prcm->cm_l3init_usbphy_clkctrl,
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&prcm->cm_clksel_usb_60mhz,
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&prcm->cm_l3init_hsusbtll_clkctrl,
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0
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};
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u32 *const clk_modules_explicit_en_essential[] = {
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&prcm->cm_wkup_gptimer1_clkctrl,
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&prcm->cm_l3init_hsmmc1_clkctrl,
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&prcm->cm_l3init_hsmmc2_clkctrl,
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&prcm->cm_l4per_gptimer2_clkctrl,
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&prcm->cm_wkup_wdtimer2_clkctrl,
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&prcm->cm_l4per_uart3_clkctrl,
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&prcm->cm_l3init_fsusb_clkctrl,
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&prcm->cm_l3init_hsusbhost_clkctrl,
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0
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};
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/* Enable optional additional functional clock for GPIO4 */
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setbits_le32(&prcm->cm_l4per_gpio4_clkctrl,
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GPIO4_CLKCTRL_OPTFCLKEN_MASK);
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/* Enable 96 MHz clock for MMC1 & MMC2 */
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setbits_le32(&prcm->cm_l3init_hsmmc1_clkctrl,
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HSMMC_CLKCTRL_CLKSEL_MASK);
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setbits_le32(&prcm->cm_l3init_hsmmc2_clkctrl,
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HSMMC_CLKCTRL_CLKSEL_MASK);
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/* Select 32KHz clock as the source of GPTIMER1 */
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setbits_le32(&prcm->cm_wkup_gptimer1_clkctrl,
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GPTIMER1_CLKCTRL_CLKSEL_MASK);
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/* Enable optional 48M functional clock for USB PHY */
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setbits_le32(&prcm->cm_l3init_usbphy_clkctrl,
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USBPHY_CLKCTRL_OPTFCLKEN_PHY_48M_MASK);
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do_enable_clocks(clk_domains_essential,
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clk_modules_hw_auto_essential,
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clk_modules_explicit_en_essential,
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1);
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}
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void enable_basic_uboot_clocks(void)
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{
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u32 *const clk_domains_essential[] = {
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0
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};
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u32 *const clk_modules_hw_auto_essential[] = {
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&prcm->cm_l3init_hsusbotg_clkctrl,
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&prcm->cm_l3init_usbphy_clkctrl,
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0
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};
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u32 *const clk_modules_explicit_en_essential[] = {
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&prcm->cm_l4per_mcspi1_clkctrl,
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&prcm->cm_l4per_i2c1_clkctrl,
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&prcm->cm_l4per_i2c2_clkctrl,
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&prcm->cm_l4per_i2c3_clkctrl,
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&prcm->cm_l4per_i2c4_clkctrl,
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0
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};
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do_enable_clocks(clk_domains_essential,
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clk_modules_hw_auto_essential,
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clk_modules_explicit_en_essential,
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1);
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}
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/*
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* Enable non-essential clock domains, modules and
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* do some additional special settings needed
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*/
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void enable_non_essential_clocks(void)
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{
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u32 *const clk_domains_non_essential[] = {
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&prcm->cm_mpu_m3_clkstctrl,
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&prcm->cm_ivahd_clkstctrl,
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&prcm->cm_dsp_clkstctrl,
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&prcm->cm_dss_clkstctrl,
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&prcm->cm_sgx_clkstctrl,
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&prcm->cm1_abe_clkstctrl,
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&prcm->cm_c2c_clkstctrl,
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&prcm->cm_cam_clkstctrl,
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&prcm->cm_dss_clkstctrl,
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&prcm->cm_sdma_clkstctrl,
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0
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};
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u32 *const clk_modules_hw_auto_non_essential[] = {
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&prcm->cm_mpu_m3_mpu_m3_clkctrl,
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&prcm->cm_ivahd_ivahd_clkctrl,
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&prcm->cm_ivahd_sl2_clkctrl,
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&prcm->cm_dsp_dsp_clkctrl,
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&prcm->cm_l3_2_gpmc_clkctrl,
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&prcm->cm_l3instr_l3_3_clkctrl,
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&prcm->cm_l3instr_l3_instr_clkctrl,
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&prcm->cm_l3instr_intrconn_wp1_clkctrl,
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&prcm->cm_l3init_hsi_clkctrl,
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&prcm->cm_l3init_hsusbtll_clkctrl,
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0
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};
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u32 *const clk_modules_explicit_en_non_essential[] = {
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&prcm->cm1_abe_aess_clkctrl,
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&prcm->cm1_abe_pdm_clkctrl,
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&prcm->cm1_abe_dmic_clkctrl,
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&prcm->cm1_abe_mcasp_clkctrl,
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&prcm->cm1_abe_mcbsp1_clkctrl,
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&prcm->cm1_abe_mcbsp2_clkctrl,
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&prcm->cm1_abe_mcbsp3_clkctrl,
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&prcm->cm1_abe_slimbus_clkctrl,
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&prcm->cm1_abe_timer5_clkctrl,
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&prcm->cm1_abe_timer6_clkctrl,
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&prcm->cm1_abe_timer7_clkctrl,
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&prcm->cm1_abe_timer8_clkctrl,
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&prcm->cm1_abe_wdt3_clkctrl,
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&prcm->cm_l4per_gptimer9_clkctrl,
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&prcm->cm_l4per_gptimer10_clkctrl,
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&prcm->cm_l4per_gptimer11_clkctrl,
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&prcm->cm_l4per_gptimer3_clkctrl,
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&prcm->cm_l4per_gptimer4_clkctrl,
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&prcm->cm_l4per_hdq1w_clkctrl,
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&prcm->cm_l4per_mcbsp4_clkctrl,
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&prcm->cm_l4per_mcspi2_clkctrl,
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&prcm->cm_l4per_mcspi3_clkctrl,
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&prcm->cm_l4per_mcspi4_clkctrl,
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&prcm->cm_l4per_mmcsd3_clkctrl,
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&prcm->cm_l4per_mmcsd4_clkctrl,
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&prcm->cm_l4per_mmcsd5_clkctrl,
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&prcm->cm_l4per_uart1_clkctrl,
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&prcm->cm_l4per_uart2_clkctrl,
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&prcm->cm_l4per_uart4_clkctrl,
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&prcm->cm_wkup_keyboard_clkctrl,
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&prcm->cm_wkup_wdtimer2_clkctrl,
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&prcm->cm_cam_iss_clkctrl,
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&prcm->cm_cam_fdif_clkctrl,
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&prcm->cm_dss_dss_clkctrl,
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&prcm->cm_sgx_sgx_clkctrl,
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&prcm->cm_l3init_hsusbhost_clkctrl,
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&prcm->cm_l3init_fsusb_clkctrl,
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0
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};
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/* Enable optional functional clock for ISS */
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setbits_le32(&prcm->cm_cam_iss_clkctrl, ISS_CLKCTRL_OPTFCLKEN_MASK);
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/* Enable all optional functional clocks of DSS */
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setbits_le32(&prcm->cm_dss_dss_clkctrl, DSS_CLKCTRL_OPTFCLKEN_MASK);
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do_enable_clocks(clk_domains_non_essential,
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clk_modules_hw_auto_non_essential,
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clk_modules_explicit_en_non_essential,
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0);
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/* Put camera module in no sleep mode */
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clrsetbits_le32(&prcm->cm_cam_clkstctrl, MODULE_CLKCTRL_MODULEMODE_MASK,
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CD_CLKCTRL_CLKTRCTRL_NO_SLEEP <<
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MODULE_CLKCTRL_MODULEMODE_SHIFT);
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}
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