mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-11 04:33:46 +09:00
3ab019e1dc
To fix the build error when build for Altera dev kit, not virtual target. At same time, set the build for Altera dev kit as default instead virtual target. With that, U-Boot is booting well and SPL still lack of few drivers. Signed-off-by: Chin Liang See <clsee@altera.com> Cc: Pavel Machek <pavel@denx.de> Cc: Marek Vasut <marex@denx.de> Cc: Tom Rini <trini@ti.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net>
256 lines
6.6 KiB
C
256 lines
6.6 KiB
C
/*
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* Copyright (C) 2012 Altera Corporation <www.altera.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#include <asm/arch/socfpga_base_addrs.h>
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#include "../../board/altera/socfpga/pinmux_config.h"
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#include "../../board/altera/socfpga/iocsr_config.h"
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#include "../../board/altera/socfpga/pll_config.h"
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/*
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* High level configuration
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*/
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/* Virtual target or real hardware */
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#undef CONFIG_SOCFPGA_VIRTUAL_TARGET
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#define CONFIG_ARMV7
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#define CONFIG_SYS_DCACHE_OFF
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#undef CONFIG_USE_IRQ
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#define CONFIG_MISC_INIT_R
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#define CONFIG_SINGLE_BOOTLOADER
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#define CONFIG_SOCFPGA
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/* base address for .text section */
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#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
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#define CONFIG_SYS_TEXT_BASE 0x08000040
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#else
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#define CONFIG_SYS_TEXT_BASE 0x01000040
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#endif
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#define CONFIG_SYS_LOAD_ADDR 0x7fc0
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/* Console I/O Buffer Size */
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#define CONFIG_SYS_CBSIZE 256
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/* Monitor Command Prompt */
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#define CONFIG_SYS_PROMPT "SOCFPGA_CYCLONE5 # "
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
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sizeof(CONFIG_SYS_PROMPT) + 16)
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/*
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* Display CPU and Board Info
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*/
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#define CONFIG_DISPLAY_CPUINFO
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#define CONFIG_DISPLAY_BOARDINFO
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/*
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* Enable early stage initialization at C environment
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*/
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#define CONFIG_BOARD_EARLY_INIT_F
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/* flat device tree */
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#define CONFIG_OF_LIBFDT
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/* skip updating the FDT blob */
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#define CONFIG_FDT_BLOB_SKIP_UPDATE
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/* Initial Memory map size for Linux, minus 4k alignment for DFT blob */
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#define CONFIG_SYS_BOOTMAPSZ ((256*1024*1024) - (4*1024))
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#define CONFIG_SPL_RAM_DEVICE
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#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR
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#define CONFIG_SYS_SPL_MALLOC_START ((unsigned long) (&__malloc_start))
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#define CONFIG_SYS_SPL_MALLOC_SIZE (&__malloc_end - &__malloc_start)
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/*
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* Memory allocation (MALLOC)
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*/
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/* Room required on the stack for the environment data */
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#define CONFIG_ENV_SIZE 1024
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/* Size of DRAM reserved for malloc() use */
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#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
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/* SP location before relocation, must use scratch RAM */
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#define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000
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/* Reserving 0x100 space at back of scratch RAM for debug info */
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#define CONFIG_SYS_INIT_RAM_SIZE (0x10000 - 0x100)
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/* Stack pointer prior relocation, must situated at on-chip RAM */
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#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
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CONFIG_SYS_INIT_RAM_SIZE - \
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GENERATED_GBL_DATA_SIZE)
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/*
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* Command line configuration.
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*/
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#define CONFIG_SYS_NO_FLASH
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#include <config_cmd_default.h>
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/* FAT file system support */
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#define CONFIG_CMD_FAT
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/*
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* Misc
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*/
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#define CONFIG_DOS_PARTITION 1
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#ifdef CONFIG_SPL_BUILD
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#undef CONFIG_PARTITIONS
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#endif
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/*
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* Environment setup
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*/
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/* Delay before automatically booting the default image */
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#define CONFIG_BOOTDELAY 3
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/* Enable auto completion of commands using TAB */
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#define CONFIG_AUTO_COMPLETE
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/* use "hush" command parser */
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#define CONFIG_SYS_HUSH_PARSER
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#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
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#define CONFIG_CMD_RUN
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#define CONFIG_BOOTCOMMAND "run ramboot"
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/*
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* arguments passed to the bootm command. The value of
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* CONFIG_BOOTARGS goes into the environment value "bootargs".
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* Do note the value will overide also the chosen node in FDT blob.
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*/
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#define CONFIG_BOOTARGS "console=ttyS0,57600,mem=256M@0x0"
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"verify=n\0" \
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"loadaddr= " __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
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"ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \
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"bootm ${loadaddr} - ${fdt_addr}\0" \
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"bootimage=uImage\0" \
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"fdt_addr=100\0" \
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"fsloadcmd=ext2load\0" \
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"bootm ${loadaddr} - ${fdt_addr}\0" \
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"qspiroot=/dev/mtdblock0\0" \
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"qspirootfstype=jffs2\0" \
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"qspiboot=setenv bootargs " CONFIG_BOOTARGS \
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" root=${qspiroot} rw rootfstype=${qspirootfstype};"\
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"bootm ${loadaddr} - ${fdt_addr}\0"
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/* using environment setting for stdin, stdout, stderr */
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#define CONFIG_SYS_CONSOLE_IS_IN_ENV
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/* Enable the call to overwrite_console() */
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#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
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/* Enable overwrite of previous console environment settings */
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#define CONFIG_SYS_CONSOLE_ENV_OVERWRITE
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/* max number of command args */
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#define CONFIG_SYS_MAXARGS 16
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/*
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* Hardware drivers
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*/
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/*
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* SDRAM Memory Map
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*/
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/* We have 1 bank of DRAM */
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#define CONFIG_NR_DRAM_BANKS 1
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/* SDRAM Bank #1 */
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#define CONFIG_SYS_SDRAM_BASE 0x00000000
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/* SDRAM memory size */
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#define PHYS_SDRAM_1_SIZE 0x40000000
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#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE
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#define CONFIG_SYS_MEMTEST_START 0x00000000
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#define CONFIG_SYS_MEMTEST_END PHYS_SDRAM_1_SIZE
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/*
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* NS16550 Configuration
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*/
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#define UART0_BASE SOCFPGA_UART0_ADDRESS
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#define CONFIG_SYS_NS16550
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#define CONFIG_SYS_NS16550_SERIAL
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#define CONFIG_SYS_NS16550_REG_SIZE -4
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#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
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#define CONFIG_CONS_INDEX 1
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#define CONFIG_SYS_NS16550_COM1 UART0_BASE
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#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, 115200}
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#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
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#define V_NS16550_CLK 1000000
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#else
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#define V_NS16550_CLK 100000000
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#endif
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#define CONFIG_BAUDRATE 115200
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/*
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* FLASH
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*/
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#define CONFIG_SYS_NO_FLASH
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/*
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* L4 OSC1 Timer 0
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*/
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/* This timer use eosc1 where the clock frequency is fixed
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* throughout any condition */
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#define CONFIG_SYS_TIMERBASE SOCFPGA_OSC1TIMER0_ADDRESS
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/* reload value when timer count to zero */
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#define TIMER_LOAD_VAL 0xFFFFFFFF
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/* Timer info */
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#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
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#define CONFIG_SYS_TIMER_RATE 2400000
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#else
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#define CONFIG_SYS_TIMER_RATE 25000000
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#endif
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#define CONFIG_SYS_TIMER_COUNTS_DOWN
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#define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMERBASE + 0x4)
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#define CONFIG_ENV_IS_NOWHERE
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/*
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* L4 Watchdog
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*/
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#define CONFIG_HW_WATCHDOG
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#define CONFIG_HW_WATCHDOG_TIMEOUT_MS 2000
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#define CONFIG_DESIGNWARE_WATCHDOG
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#define CONFIG_DW_WDT_BASE SOCFPGA_L4WD0_ADDRESS
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/* Clocks source frequency to watchdog timer */
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#define CONFIG_DW_WDT_CLOCK_KHZ 25000
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/*
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* SPL "Second Program Loader" aka Initial Software
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*/
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/* Enable building of SPL globally */
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#define CONFIG_SPL_FRAMEWORK
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/* TEXT_BASE for linking the SPL binary */
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#define CONFIG_SPL_TEXT_BASE 0xFFFF0000
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/* Stack size for SPL */
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#define CONFIG_SPL_STACK_SIZE (4 * 1024)
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/* MALLOC size for SPL */
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#define CONFIG_SPL_MALLOC_SIZE (5 * 1024)
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#define CONFIG_SPL_SERIAL_SUPPORT
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#define CONFIG_SPL_BOARD_INIT
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#define CHUNKSZ_CRC32 (1 * 1024)
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#define CONFIG_CRC32_VERIFY
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/* Linker script for SPL */
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#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv7/socfpga/u-boot-spl.lds"
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/* Support for common/libcommon.o in SPL binary */
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#define CONFIG_SPL_LIBCOMMON_SUPPORT
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/* Support for lib/libgeneric.o in SPL binary */
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#define CONFIG_SPL_LIBGENERIC_SUPPORT
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/* Support for watchdog */
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#define CONFIG_SPL_WATCHDOG_SUPPORT
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#endif /* __CONFIG_H */
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