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https://github.com/brain-hackers/u-boot-brain
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3a94d75d0e
dwmmc controller has default internal divider by 2, and we always provide double of the clock rate request by dwmmc controller. Sync code for all Rockchip SoC with: 4055b46 rockchip: clk: rk3288: fix mmc clock setting Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> [fixup for 'missing DIV_ROUND_UP' conflict for clk_rk3288.c:] Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> |
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| .. | ||
| aspeed | ||
| at91 | ||
| exynos | ||
| renesas | ||
| rockchip | ||
| tegra | ||
| uniphier | ||
| clk_bcm6345.c | ||
| clk_boston.c | ||
| clk_fixed_rate.c | ||
| clk_pic32.c | ||
| clk_sandbox_test.c | ||
| clk_sandbox.c | ||
| clk_stm32f7.c | ||
| clk_zynq.c | ||
| clk_zynqmp.c | ||
| clk-uclass.c | ||
| Kconfig | ||
| Makefile | ||