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GP EVM has 1GB DDR3 attached(Part no: MT41K512M8RH). Adding details for the same. Below is the brief description of DDR3 init sequence(SW leveling): -> Enable VTT regulator -> Configure VTP -> Configure DDR IO settings -> Disable initialization and refreshes until EMIF registers are programmed. -> Program Timing registers -> Program leveling registers -> Program PHY control and Temp alert and ZQ config registers. -> Enable initialization and refreshes and configure SDRAM CONFIG register Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> |
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| .. | ||
| clock_ti81xx.h | ||
| clock.h | ||
| clocks_am33xx.h | ||
| cpu.h | ||
| ddr_defs.h | ||
| gpio.h | ||
| hardware_am33xx.h | ||
| hardware_am43xx.h | ||
| hardware_ti814x.h | ||
| hardware_ti816x.h | ||
| hardware.h | ||
| i2c.h | ||
| mem.h | ||
| mmc_host_def.h | ||
| mux_am33xx.h | ||
| mux_am43xx.h | ||
| mux_ti814x.h | ||
| mux_ti816x.h | ||
| mux.h | ||
| omap_gpmc.h | ||
| omap.h | ||
| spl.h | ||
| sys_proto.h | ||