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![Claudiu Beznea](/assets/img/avatar_default.png)
Add clk-peripheral compatible with common clock framework. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
255 lines
6.0 KiB
C
255 lines
6.0 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Peripheral clock support for AT91 architectures.
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*
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* Copyright (C) 2020 Microchip Technology Inc. and its subsidiaries
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*
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* Author: Claudiu Beznea <claudiu.beznea@microchip.com>
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*
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* Based on drivers/clk/at91/clk-peripheral.c from Linux.
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*/
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#include <common.h>
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#include <clk-uclass.h>
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#include <dm.h>
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#include <linux/io.h>
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#include <linux/clk-provider.h>
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#include <linux/clk/at91_pmc.h>
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#include "pmc.h"
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#define UBOOT_DM_CLK_AT91_PERIPH "at91-periph-clk"
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#define UBOOT_DM_CLK_AT91_SAM9X5_PERIPH "at91-sam9x5-periph-clk"
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#define PERIPHERAL_ID_MIN 2
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#define PERIPHERAL_ID_MAX 31
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#define PERIPHERAL_MASK(id) (1 << ((id) & PERIPHERAL_ID_MAX))
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#define PERIPHERAL_MAX_SHIFT 3
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struct clk_peripheral {
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void __iomem *base;
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struct clk clk;
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u32 id;
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};
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#define to_clk_peripheral(_c) container_of(_c, struct clk_peripheral, clk)
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struct clk_sam9x5_peripheral {
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const struct clk_pcr_layout *layout;
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void __iomem *base;
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struct clk clk;
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struct clk_range range;
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u32 id;
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u32 div;
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bool auto_div;
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};
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#define to_clk_sam9x5_peripheral(_c) \
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container_of(_c, struct clk_sam9x5_peripheral, clk)
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static int clk_peripheral_enable(struct clk *clk)
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{
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struct clk_peripheral *periph = to_clk_peripheral(clk);
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int offset = AT91_PMC_PCER;
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u32 id = periph->id;
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if (id < PERIPHERAL_ID_MIN)
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return 0;
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if (id > PERIPHERAL_ID_MAX)
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offset = AT91_PMC_PCER1;
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pmc_write(periph->base, offset, PERIPHERAL_MASK(id));
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return 0;
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}
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static int clk_peripheral_disable(struct clk *clk)
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{
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struct clk_peripheral *periph = to_clk_peripheral(clk);
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int offset = AT91_PMC_PCDR;
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u32 id = periph->id;
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if (id < PERIPHERAL_ID_MIN)
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return -EINVAL;
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if (id > PERIPHERAL_ID_MAX)
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offset = AT91_PMC_PCDR1;
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pmc_write(periph->base, offset, PERIPHERAL_MASK(id));
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return 0;
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}
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static const struct clk_ops peripheral_ops = {
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.enable = clk_peripheral_enable,
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.disable = clk_peripheral_disable,
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.get_rate = clk_generic_get_rate,
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};
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struct clk *
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at91_clk_register_peripheral(void __iomem *base, const char *name,
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const char *parent_name, u32 id)
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{
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struct clk_peripheral *periph;
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struct clk *clk;
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int ret;
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if (!base || !name || !parent_name || id > PERIPHERAL_ID_MAX)
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return ERR_PTR(-EINVAL);
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periph = kzalloc(sizeof(*periph), GFP_KERNEL);
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if (!periph)
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return ERR_PTR(-ENOMEM);
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periph->id = id;
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periph->base = base;
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clk = &periph->clk;
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clk->flags = CLK_GET_RATE_NOCACHE;
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ret = clk_register(clk, UBOOT_DM_CLK_AT91_PERIPH, name, parent_name);
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if (ret) {
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kfree(periph);
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clk = ERR_PTR(ret);
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}
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return clk;
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}
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U_BOOT_DRIVER(at91_periph_clk) = {
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.name = UBOOT_DM_CLK_AT91_PERIPH,
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.id = UCLASS_CLK,
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.ops = &peripheral_ops,
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.flags = DM_FLAG_PRE_RELOC,
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};
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static int clk_sam9x5_peripheral_enable(struct clk *clk)
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{
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struct clk_sam9x5_peripheral *periph = to_clk_sam9x5_peripheral(clk);
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if (periph->id < PERIPHERAL_ID_MIN)
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return 0;
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pmc_write(periph->base, periph->layout->offset,
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(periph->id & periph->layout->pid_mask));
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pmc_update_bits(periph->base, periph->layout->offset,
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periph->layout->cmd | AT91_PMC_PCR_EN,
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periph->layout->cmd | AT91_PMC_PCR_EN);
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return 0;
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}
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static int clk_sam9x5_peripheral_disable(struct clk *clk)
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{
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struct clk_sam9x5_peripheral *periph = to_clk_sam9x5_peripheral(clk);
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if (periph->id < PERIPHERAL_ID_MIN)
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return -EINVAL;
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pmc_write(periph->base, periph->layout->offset,
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(periph->id & periph->layout->pid_mask));
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pmc_update_bits(periph->base, periph->layout->offset,
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AT91_PMC_PCR_EN | periph->layout->cmd,
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periph->layout->cmd);
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return 0;
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}
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static ulong clk_sam9x5_peripheral_get_rate(struct clk *clk)
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{
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struct clk_sam9x5_peripheral *periph = to_clk_sam9x5_peripheral(clk);
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ulong parent_rate = clk_get_parent_rate(clk);
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u32 val, shift = ffs(periph->layout->div_mask) - 1;
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if (!parent_rate)
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return 0;
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pmc_write(periph->base, periph->layout->offset,
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(periph->id & periph->layout->pid_mask));
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pmc_read(periph->base, periph->layout->offset, &val);
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shift = (val & periph->layout->div_mask) >> shift;
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return parent_rate >> shift;
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}
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static ulong clk_sam9x5_peripheral_set_rate(struct clk *clk, ulong rate)
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{
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struct clk_sam9x5_peripheral *periph = to_clk_sam9x5_peripheral(clk);
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ulong parent_rate = clk_get_parent_rate(clk);
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int shift;
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if (!parent_rate)
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return 0;
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if (periph->id < PERIPHERAL_ID_MIN || !periph->range.max) {
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if (parent_rate == rate)
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return rate;
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else
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return 0;
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}
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if (periph->range.max && rate > periph->range.max)
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return 0;
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for (shift = 0; shift <= PERIPHERAL_MAX_SHIFT; shift++) {
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if (parent_rate >> shift <= rate)
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break;
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}
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if (shift == PERIPHERAL_MAX_SHIFT + 1)
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return 0;
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pmc_write(periph->base, periph->layout->offset,
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(periph->id & periph->layout->pid_mask));
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pmc_update_bits(periph->base, periph->layout->offset,
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periph->layout->div_mask | periph->layout->cmd,
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(shift << (ffs(periph->layout->div_mask) - 1)) |
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periph->layout->cmd);
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return parent_rate >> shift;
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}
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static const struct clk_ops sam9x5_peripheral_ops = {
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.enable = clk_sam9x5_peripheral_enable,
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.disable = clk_sam9x5_peripheral_disable,
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.get_rate = clk_sam9x5_peripheral_get_rate,
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.set_rate = clk_sam9x5_peripheral_set_rate,
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};
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struct clk *
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at91_clk_register_sam9x5_peripheral(void __iomem *base,
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const struct clk_pcr_layout *layout,
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const char *name, const char *parent_name,
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u32 id, const struct clk_range *range)
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{
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struct clk_sam9x5_peripheral *periph;
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struct clk *clk;
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int ret;
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if (!base || !layout || !name || !parent_name || !range)
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return ERR_PTR(-EINVAL);
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periph = kzalloc(sizeof(*periph), GFP_KERNEL);
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if (!periph)
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return ERR_PTR(-ENOMEM);
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periph->id = id;
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periph->base = base;
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periph->layout = layout;
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periph->range = *range;
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clk = &periph->clk;
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clk->flags = CLK_GET_RATE_NOCACHE;
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ret = clk_register(clk, UBOOT_DM_CLK_AT91_SAM9X5_PERIPH, name,
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parent_name);
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if (ret) {
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kfree(periph);
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clk = ERR_PTR(ret);
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}
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return clk;
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}
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U_BOOT_DRIVER(at91_sam9x5_periph_clk) = {
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.name = UBOOT_DM_CLK_AT91_SAM9X5_PERIPH,
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.id = UCLASS_CLK,
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.ops = &sam9x5_peripheral_ops,
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.flags = DM_FLAG_PRE_RELOC,
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};
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