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![Yangbo Lu](/assets/img/avatar_default.png)
Converted to use fsl_esdhc_imx for i.MX platforms. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Tested-by: Steffen Dirkwinkel <s.dirkwinkel@beckhoff.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Lukasz Majewski <lukma@denx.de> Reviewed-by: Martyn Welch <martyn.welch@collabora.com> Acked-by: Jason Liu <Jason.hui.liu@nxp.com>
211 lines
5.9 KiB
C
211 lines
5.9 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* SPL board functions for CompuLab CL-SOM-iMX7 module
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*
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* (C) Copyright 2017 CompuLab, Ltd. http://www.compulab.com
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*
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* Author: Uri Mashiach <uri.mashiach@compulab.co.il>
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*/
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#include <common.h>
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#include <spl.h>
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#include <fsl_esdhc_imx.h>
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#include <asm/mach-imx/iomux-v3.h>
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#include <asm/arch-mx7/mx7-pins.h>
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#include <asm/arch-mx7/clock.h>
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#include <asm/arch-mx7/mx7-ddr.h>
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#include "common.h"
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#ifdef CONFIG_FSL_ESDHC_IMX
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static struct fsl_esdhc_cfg cl_som_imx7_spl_usdhc_cfg = {
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USDHC1_BASE_ADDR, 0, 4};
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int board_mmc_init(bd_t *bis)
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{
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cl_som_imx7_usdhc1_pads_set();
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cl_som_imx7_spl_usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
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return fsl_esdhc_initialize(bis, &cl_som_imx7_spl_usdhc_cfg);
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}
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#endif /* CONFIG_FSL_ESDHC_IMX */
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static iomux_v3_cfg_t const led_pads[] = {
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MX7D_PAD_SAI1_TX_SYNC__GPIO6_IO14 | MUX_PAD_CTRL(PAD_CTL_PUS_PU5KOHM |
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PAD_CTL_PUE | PAD_CTL_SRE_SLOW)
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};
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static struct ddrc cl_som_imx7_spl_ddrc_regs_val = {
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.init1 = 0x00690000,
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.init0 = 0x00020083,
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.init3 = 0x09300004,
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.init4 = 0x04080000,
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.init5 = 0x00100004,
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.rankctl = 0x0000033F,
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.dramtmg1 = 0x0007020E,
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.dramtmg2 = 0x03040407,
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.dramtmg3 = 0x00002006,
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.dramtmg4 = 0x04020305,
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.dramtmg5 = 0x03030202,
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.dramtmg8 = 0x00000803,
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.zqctl0 = 0x00810021,
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.dfitmg0 = 0x02098204,
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.dfitmg1 = 0x00030303,
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.dfiupd0 = 0x80400003,
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.dfiupd1 = 0x00100020,
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.dfiupd2 = 0x80100004,
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.addrmap4 = 0x00000F0F,
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.odtcfg = 0x06000604,
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.odtmap = 0x00000001,
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};
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static struct ddrc_mp cl_som_imx7_spl_ddrc_mp_val = {
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.pctrl_0 = 0x00000001,
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};
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static struct ddr_phy cl_som_imx7_spl_ddr_phy_regs_val = {
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.phy_con0 = 0x17420F40,
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.phy_con1 = 0x10210100,
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.phy_con4 = 0x00060807,
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.mdll_con0 = 0x1010007E,
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.drvds_con0 = 0x00000D6E,
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.cmd_sdll_con0 = 0x00000010,
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.offset_lp_con0 = 0x0000000F,
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};
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struct mx7_calibration cl_som_imx7_spl_calib_param = {
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.num_val = 5,
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.values = {
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0x0E407304,
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0x0E447304,
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0x0E447306,
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0x0E447304,
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0x0E407304,
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},
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};
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static void cl_som_imx7_spl_dram_cfg_size(u32 ram_size)
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{
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switch (ram_size) {
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case SZ_256M:
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cl_som_imx7_spl_ddrc_regs_val.mstr = 0x01041001;
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cl_som_imx7_spl_ddrc_regs_val.rfshtmg = 0x00400046;
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cl_som_imx7_spl_ddrc_regs_val.dramtmg0 = 0x090E1109;
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cl_som_imx7_spl_ddrc_regs_val.addrmap0 = 0x00000014;
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cl_som_imx7_spl_ddrc_regs_val.addrmap1 = 0x00151515;
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cl_som_imx7_spl_ddrc_regs_val.addrmap5 = 0x03030303;
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cl_som_imx7_spl_ddrc_regs_val.addrmap6 = 0x0F0F0303;
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cl_som_imx7_spl_ddr_phy_regs_val.offset_rd_con0 = 0x0C0C0C0C;
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cl_som_imx7_spl_ddr_phy_regs_val.offset_wr_con0 = 0x04040404;
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break;
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case SZ_512M:
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cl_som_imx7_spl_ddrc_regs_val.mstr = 0x01040001;
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cl_som_imx7_spl_ddrc_regs_val.rfshtmg = 0x00400046;
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cl_som_imx7_spl_ddrc_regs_val.dramtmg0 = 0x090E1109;
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cl_som_imx7_spl_ddrc_regs_val.addrmap0 = 0x00000015;
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cl_som_imx7_spl_ddrc_regs_val.addrmap1 = 0x00161616;
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cl_som_imx7_spl_ddrc_regs_val.addrmap5 = 0x04040404;
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cl_som_imx7_spl_ddrc_regs_val.addrmap6 = 0x0F0F0404;
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cl_som_imx7_spl_ddr_phy_regs_val.offset_rd_con0 = 0x0C0C0C0C;
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cl_som_imx7_spl_ddr_phy_regs_val.offset_wr_con0 = 0x04040404;
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break;
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case SZ_1G:
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cl_som_imx7_spl_ddrc_regs_val.mstr = 0x01040001;
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cl_som_imx7_spl_ddrc_regs_val.rfshtmg = 0x00400046;
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cl_som_imx7_spl_ddrc_regs_val.dramtmg0 = 0x090E1109;
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cl_som_imx7_spl_ddrc_regs_val.addrmap0 = 0x00000016;
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cl_som_imx7_spl_ddrc_regs_val.addrmap1 = 0x00171717;
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cl_som_imx7_spl_ddrc_regs_val.addrmap5 = 0x04040404;
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cl_som_imx7_spl_ddrc_regs_val.addrmap6 = 0x0F040404;
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cl_som_imx7_spl_ddr_phy_regs_val.offset_rd_con0 = 0x0A0A0A0A;
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cl_som_imx7_spl_ddr_phy_regs_val.offset_wr_con0 = 0x02020202;
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break;
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case SZ_2G:
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cl_som_imx7_spl_ddrc_regs_val.mstr = 0x01040001;
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cl_som_imx7_spl_ddrc_regs_val.rfshtmg = 0x0040005E;
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cl_som_imx7_spl_ddrc_regs_val.dramtmg0 = 0x090E110A;
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cl_som_imx7_spl_ddrc_regs_val.addrmap0 = 0x00000018;
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cl_som_imx7_spl_ddrc_regs_val.addrmap1 = 0x00181818;
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cl_som_imx7_spl_ddrc_regs_val.addrmap5 = 0x04040404;
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cl_som_imx7_spl_ddrc_regs_val.addrmap6 = 0x04040404;
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cl_som_imx7_spl_ddr_phy_regs_val.offset_rd_con0 = 0x0A0A0A0A;
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cl_som_imx7_spl_ddr_phy_regs_val.offset_wr_con0 = 0x04040404;
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break;
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}
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mx7_dram_cfg(&cl_som_imx7_spl_ddrc_regs_val,
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&cl_som_imx7_spl_ddrc_mp_val,
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&cl_som_imx7_spl_ddr_phy_regs_val,
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&cl_som_imx7_spl_calib_param);
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}
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static void cl_som_imx7_spl_dram_cfg(void)
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{
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ulong ram_size_test, ram_size = 0;
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for (ram_size = SZ_2G; ram_size >= SZ_256M; ram_size >>= 1) {
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cl_som_imx7_spl_dram_cfg_size(ram_size);
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ram_size_test = get_ram_size((long int *)PHYS_SDRAM, ram_size);
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if (ram_size_test == ram_size)
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break;
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}
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if (ram_size < SZ_256M) {
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puts("!!!ERROR!!! DRAM detection failed!!!\n");
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hang();
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}
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}
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#ifdef CONFIG_SPL_SPI_SUPPORT
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static void cl_som_imx7_spl_spi_init(void)
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{
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cl_som_imx7_espi1_pads_set();
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}
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#else /* !CONFIG_SPL_SPI_SUPPORT */
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static void cl_som_imx7_spl_spi_init(void) {}
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#endif /* CONFIG_SPL_SPI_SUPPORT */
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void board_init_f(ulong dummy)
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{
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imx_iomux_v3_setup_multiple_pads(led_pads, 1);
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/* setup AIPS and disable watchdog */
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arch_cpu_init();
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/* setup GP timer */
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timer_init();
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cl_som_imx7_spl_spi_init();
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cl_som_imx7_uart1_pads_set();
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/* UART clocks enabled and gd valid - init serial console */
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preloader_console_init();
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/* DRAM detection */
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cl_som_imx7_spl_dram_cfg();
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/* Clear the BSS. */
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memset(__bss_start, 0, __bss_end - __bss_start);
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/* load/boot image from boot device */
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board_init_r(NULL, 0);
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}
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void spl_board_init(void)
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{
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u32 boot_device = spl_boot_device();
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if (boot_device == BOOT_DEVICE_SPI)
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puts("Booting from SPI flash\n");
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else if (boot_device == BOOT_DEVICE_MMC1)
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puts("Booting from SD card\n");
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else
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puts("Unknown boot device\n");
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}
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void board_boot_order(u32 *spl_boot_list)
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{
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spl_boot_list[0] = spl_boot_device();
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switch (spl_boot_list[0]) {
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case BOOT_DEVICE_SPI:
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spl_boot_list[1] = BOOT_DEVICE_MMC1;
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break;
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case BOOT_DEVICE_MMC1:
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spl_boot_list[1] = BOOT_DEVICE_SPI;
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break;
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}
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}
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