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![Marek Vasut](/assets/img/avatar_default.png)
Signed-off-by: Marek Vasut <marex@denx.de> Cc: Bryan Hundven <bryanhundven@gmail.com> Cc: Michael Schwingen <rincewind@discworld.dascon.de> Cc: Wolfgang Denk <wd@denx.de> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: U-Boot DM <u-boot-dm@lists.denx.de> Cc: Joe Hershberger <joe.hershberger@ni.com>
894 lines
25 KiB
C
894 lines
25 KiB
C
/**
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* @file IxNpeDlNpeMgrEcRegisters_p.h
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*
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* @author Intel Corporation
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* @date 14 December 2001
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*
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* @par
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* IXP400 SW Release version 2.0
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*
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* -- Copyright Notice --
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*
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* @par
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* Copyright 2001-2005, Intel Corporation.
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* All rights reserved.
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*
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* @par
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of the Intel Corporation nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* @par
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* @par
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* -- End of Copyright Notice --
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*/
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#ifndef IXNPEDLNPEMGRECREGISTERS_P_H
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#define IXNPEDLNPEMGRECREGISTERS_P_H
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#include "IxOsal.h"
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/*
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* Base Memory Addresses for accessing NPE registers
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*/
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#define IX_NPEDL_NPE_BASE (IX_OSAL_IXP400_PERIPHERAL_PHYS_BASE)
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#define IX_NPEDL_NPEA_OFFSET (0x6000) /**< NPE-A register base offset */
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#define IX_NPEDL_NPEB_OFFSET (0x7000) /**< NPE-B register base offset */
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#define IX_NPEDL_NPEC_OFFSET (0x8000) /**< NPE-C register base offset */
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/**
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* @def IX_NPEDL_NPEBASEADDRESS_NPEA
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* @brief Base Memory Address of NPE-A Configuration Bus registers
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*/
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#define IX_NPEDL_NPEBASEADDRESS_NPEA (IX_NPEDL_NPE_BASE + IX_NPEDL_NPEA_OFFSET)
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/**
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* @def IX_NPEDL_NPEBASEADDRESS_NPEB
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* @brief Base Memory Address of NPE-B Configuration Bus registers
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*/
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#define IX_NPEDL_NPEBASEADDRESS_NPEB (IX_NPEDL_NPE_BASE + IX_NPEDL_NPEB_OFFSET)
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/**
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* @def IX_NPEDL_NPEBASEADDRESS_NPEC
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* @brief Base Memory Address of NPE-C Configuration Bus registers
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*/
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#define IX_NPEDL_NPEBASEADDRESS_NPEC (IX_NPEDL_NPE_BASE + IX_NPEDL_NPEC_OFFSET)
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/*
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* Instruction Memory Size (in words) for each NPE
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*/
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/**
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* @def IX_NPEDL_INS_MEMSIZE_WORDS_NPEA
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* @brief Size (in words) of NPE-A Instruction Memory
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*/
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#define IX_NPEDL_INS_MEMSIZE_WORDS_NPEA 4096
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/**
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* @def IX_NPEDL_INS_MEMSIZE_WORDS_NPEB
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* @brief Size (in words) of NPE-B Instruction Memory
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*/
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#define IX_NPEDL_INS_MEMSIZE_WORDS_NPEB 2048
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/**
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* @def IX_NPEDL_INS_MEMSIZE_WORDS_NPEC
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* @brief Size (in words) of NPE-B Instruction Memory
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*/
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#define IX_NPEDL_INS_MEMSIZE_WORDS_NPEC 2048
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/*
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* Data Memory Size (in words) for each NPE
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*/
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/**
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* @def IX_NPEDL_DATA_MEMSIZE_WORDS_NPEA
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* @brief Size (in words) of NPE-A Data Memory
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*/
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#define IX_NPEDL_DATA_MEMSIZE_WORDS_NPEA 2048
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/**
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* @def IX_NPEDL_DATA_MEMSIZE_WORDS_NPEB
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* @brief Size (in words) of NPE-B Data Memory
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*/
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#define IX_NPEDL_DATA_MEMSIZE_WORDS_NPEB 2048
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/**
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* @def IX_NPEDL_DATA_MEMSIZE_WORDS_NPEC
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* @brief Size (in words) of NPE-C Data Memory
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*/
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#define IX_NPEDL_DATA_MEMSIZE_WORDS_NPEC 2048
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/*
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* Configuration Bus Register offsets (in bytes) from NPE Base Address
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*/
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/**
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* @def IX_NPEDL_REG_OFFSET_EXAD
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* @brief Offset (in bytes) of EXAD (Execution Address) register from NPE Base
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* Address
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*/
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#define IX_NPEDL_REG_OFFSET_EXAD 0x00000000
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/**
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* @def IX_NPEDL_REG_OFFSET_EXDATA
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* @brief Offset (in bytes) of EXDATA (Execution Data) register from NPE Base
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* Address
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*/
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#define IX_NPEDL_REG_OFFSET_EXDATA 0x00000004
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/**
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* @def IX_NPEDL_REG_OFFSET_EXCTL
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* @brief Offset (in bytes) of EXCTL (Execution Control) register from NPE Base
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* Address
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*/
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#define IX_NPEDL_REG_OFFSET_EXCTL 0x00000008
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/**
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* @def IX_NPEDL_REG_OFFSET_EXCT
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* @brief Offset (in bytes) of EXCT (Execution Count) register from NPE Base
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* Address
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*/
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#define IX_NPEDL_REG_OFFSET_EXCT 0x0000000C
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/**
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* @def IX_NPEDL_REG_OFFSET_AP0
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* @brief Offset (in bytes) of AP0 (Action Point 0) register from NPE Base
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* Address
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*/
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#define IX_NPEDL_REG_OFFSET_AP0 0x00000010
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/**
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* @def IX_NPEDL_REG_OFFSET_AP1
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* @brief Offset (in bytes) of AP1 (Action Point 1) register from NPE Base
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* Address
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*/
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#define IX_NPEDL_REG_OFFSET_AP1 0x00000014
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/**
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* @def IX_NPEDL_REG_OFFSET_AP2
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* @brief Offset (in bytes) of AP2 (Action Point 2) register from NPE Base
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* Address
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*/
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#define IX_NPEDL_REG_OFFSET_AP2 0x00000018
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/**
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* @def IX_NPEDL_REG_OFFSET_AP3
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* @brief Offset (in bytes) of AP3 (Action Point 3) register from NPE Base
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* Address
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*/
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#define IX_NPEDL_REG_OFFSET_AP3 0x0000001C
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/**
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* @def IX_NPEDL_REG_OFFSET_WFIFO
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* @brief Offset (in bytes) of WFIFO (Watchpoint FIFO) register from NPE Base
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* Address
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*/
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#define IX_NPEDL_REG_OFFSET_WFIFO 0x00000020
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/**
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* @def IX_NPEDL_REG_OFFSET_WC
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* @brief Offset (in bytes) of WC (Watch Count) register from NPE Base
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* Address
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*/
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#define IX_NPEDL_REG_OFFSET_WC 0x00000024
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/**
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* @def IX_NPEDL_REG_OFFSET_PROFCT
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* @brief Offset (in bytes) of PROFCT (Profile Count) register from NPE Base
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* Address
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*/
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#define IX_NPEDL_REG_OFFSET_PROFCT 0x00000028
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/**
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* @def IX_NPEDL_REG_OFFSET_STAT
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* @brief Offset (in bytes) of STAT (Messaging Status) register from NPE Base
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* Address
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*/
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#define IX_NPEDL_REG_OFFSET_STAT 0x0000002C
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/**
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* @def IX_NPEDL_REG_OFFSET_CTL
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* @brief Offset (in bytes) of CTL (Messaging Control) register from NPE Base
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* Address
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*/
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#define IX_NPEDL_REG_OFFSET_CTL 0x00000030
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/**
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* @def IX_NPEDL_REG_OFFSET_MBST
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* @brief Offset (in bytes) of MBST (Mailbox Status) register from NPE Base
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* Address
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*/
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#define IX_NPEDL_REG_OFFSET_MBST 0x00000034
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/**
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* @def IX_NPEDL_REG_OFFSET_FIFO
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* @brief Offset (in bytes) of FIFO (messaging in/out FIFO) register from NPE
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* Base Address
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*/
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#define IX_NPEDL_REG_OFFSET_FIFO 0x00000038
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/*
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* Non-zero reset values for the Configuration Bus registers
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*/
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/**
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* @def IX_NPEDL_REG_RESET_FIFO
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* @brief Reset value for Mailbox (MBST) register
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* NOTE that if used, it should be complemented with an NPE intruction
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* to clear the Mailbox at the NPE side as well
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*/
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#define IX_NPEDL_REG_RESET_MBST 0x0000F0F0
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/*
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* Bit-masks used to read/write particular bits in Configuration Bus registers
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*/
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/**
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* @def IX_NPEDL_MASK_WFIFO_VALID
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* @brief Masks the VALID bit in the WFIFO register
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*/
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#define IX_NPEDL_MASK_WFIFO_VALID 0x80000000
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/**
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* @def IX_NPEDL_MASK_STAT_OFNE
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* @brief Masks the OFNE bit in the STAT register
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*/
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#define IX_NPEDL_MASK_STAT_OFNE 0x00010000
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/**
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* @def IX_NPEDL_MASK_STAT_IFNE
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* @brief Masks the IFNE bit in the STAT register
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*/
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#define IX_NPEDL_MASK_STAT_IFNE 0x00080000
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/*
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* EXCTL (Execution Control) Register commands
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*/
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/**
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* @def IX_NPEDL_EXCTL_CMD_NPE_STEP
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* @brief EXCTL Command to Step execution of an NPE Instruction
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*/
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#define IX_NPEDL_EXCTL_CMD_NPE_STEP 0x01
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/**
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* @def IX_NPEDL_EXCTL_CMD_NPE_START
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* @brief EXCTL Command to Start NPE execution
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*/
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#define IX_NPEDL_EXCTL_CMD_NPE_START 0x02
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/**
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* @def IX_NPEDL_EXCTL_CMD_NPE_STOP
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* @brief EXCTL Command to Stop NPE execution
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*/
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#define IX_NPEDL_EXCTL_CMD_NPE_STOP 0x03
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/**
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* @def IX_NPEDL_EXCTL_CMD_NPE_CLR_PIPE
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* @brief EXCTL Command to Clear NPE instruction pipeline
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*/
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#define IX_NPEDL_EXCTL_CMD_NPE_CLR_PIPE 0x04
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/**
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* @def IX_NPEDL_EXCTL_CMD_RD_INS_MEM
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* @brief EXCTL Command to read NPE instruction memory at address in EXAD
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* register and return value in EXDATA register
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*/
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#define IX_NPEDL_EXCTL_CMD_RD_INS_MEM 0x10
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/**
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* @def IX_NPEDL_EXCTL_CMD_WR_INS_MEM
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* @brief EXCTL Command to write NPE instruction memory at address in EXAD
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* register with data in EXDATA register
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*/
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#define IX_NPEDL_EXCTL_CMD_WR_INS_MEM 0x11
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/**
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* @def IX_NPEDL_EXCTL_CMD_RD_DATA_MEM
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* @brief EXCTL Command to read NPE data memory at address in EXAD
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* register and return value in EXDATA register
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*/
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#define IX_NPEDL_EXCTL_CMD_RD_DATA_MEM 0x12
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/**
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* @def IX_NPEDL_EXCTL_CMD_WR_DATA_MEM
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* @brief EXCTL Command to write NPE data memory at address in EXAD
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* register with data in EXDATA register
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*/
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#define IX_NPEDL_EXCTL_CMD_WR_DATA_MEM 0x13
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/**
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* @def IX_NPEDL_EXCTL_CMD_RD_ECS_REG
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* @brief EXCTL Command to read Execution Access register at address in EXAD
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* register and return value in EXDATA register
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*/
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#define IX_NPEDL_EXCTL_CMD_RD_ECS_REG 0x14
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/**
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* @def IX_NPEDL_EXCTL_CMD_WR_ECS_REG
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* @brief EXCTL Command to write Execution Access register at address in EXAD
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* register with data in EXDATA register
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*/
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#define IX_NPEDL_EXCTL_CMD_WR_ECS_REG 0x15
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/**
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* @def IX_NPEDL_EXCTL_CMD_CLR_PROFILE_CNT
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* @brief EXCTL Command to clear Profile Count register
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*/
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#define IX_NPEDL_EXCTL_CMD_CLR_PROFILE_CNT 0x0C
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/*
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* EXCTL (Execution Control) Register status bit masks
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*/
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/**
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* @def IX_NPEDL_EXCTL_STATUS_RUN
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* @brief Masks the RUN status bit in the EXCTL register
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*/
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#define IX_NPEDL_EXCTL_STATUS_RUN 0x80000000
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/**
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* @def IX_NPEDL_EXCTL_STATUS_STOP
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* @brief Masks the STOP status bit in the EXCTL register
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*/
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#define IX_NPEDL_EXCTL_STATUS_STOP 0x40000000
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/**
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* @def IX_NPEDL_EXCTL_STATUS_CLEAR
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* @brief Masks the CLEAR status bit in the EXCTL register
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*/
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#define IX_NPEDL_EXCTL_STATUS_CLEAR 0x20000000
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/**
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* @def IX_NPEDL_EXCTL_STATUS_ECS_K
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* @brief Masks the K (pipeline Klean) status bit in the EXCTL register
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*/
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#define IX_NPEDL_EXCTL_STATUS_ECS_K 0x00800000
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/*
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* Executing Context Stack (ECS) level registers
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*/
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/**
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* @def IX_NPEDL_ECS_BG_CTXT_REG_0
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* @brief Execution Access register address for register 0 at Backgound
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* Executing Context Stack level
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*/
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#define IX_NPEDL_ECS_BG_CTXT_REG_0 0x00
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/**
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* @def IX_NPEDL_ECS_BG_CTXT_REG_1
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* @brief Execution Access register address for register 1 at Backgound
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* Executing Context Stack level
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*/
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#define IX_NPEDL_ECS_BG_CTXT_REG_1 0x01
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/**
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* @def IX_NPEDL_ECS_BG_CTXT_REG_2
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* @brief Execution Access register address for register 2 at Backgound
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* Executing Context Stack level
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*/
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#define IX_NPEDL_ECS_BG_CTXT_REG_2 0x02
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/**
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* @def IX_NPEDL_ECS_PRI_1_CTXT_REG_0
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* @brief Execution Access register address for register 0 at Priority 1
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* Executing Context Stack level
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*/
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#define IX_NPEDL_ECS_PRI_1_CTXT_REG_0 0x04
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/**
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* @def IX_NPEDL_ECS_PRI_1_CTXT_REG_1
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* @brief Execution Access register address for register 1 at Priority 1
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* Executing Context Stack level
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*/
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#define IX_NPEDL_ECS_PRI_1_CTXT_REG_1 0x05
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/**
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* @def IX_NPEDL_ECS_PRI_1_CTXT_REG_2
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* @brief Execution Access register address for register 2 at Priority 1
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* Executing Context Stack level
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*/
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#define IX_NPEDL_ECS_PRI_1_CTXT_REG_2 0x06
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/**
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* @def IX_NPEDL_ECS_PRI_2_CTXT_REG_0
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* @brief Execution Access register address for register 0 at Priority 2
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* Executing Context Stack level
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*/
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#define IX_NPEDL_ECS_PRI_2_CTXT_REG_0 0x08
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/**
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* @def IX_NPEDL_ECS_PRI_2_CTXT_REG_1
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* @brief Execution Access register address for register 1 at Priority 2
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* Executing Context Stack level
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*/
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#define IX_NPEDL_ECS_PRI_2_CTXT_REG_1 0x09
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/**
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* @def IX_NPEDL_ECS_PRI_2_CTXT_REG_2
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* @brief Execution Access register address for register 2 at Priority 2
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* Executing Context Stack level
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*/
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#define IX_NPEDL_ECS_PRI_2_CTXT_REG_2 0x0A
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/**
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* @def IX_NPEDL_ECS_DBG_CTXT_REG_0
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* @brief Execution Access register address for register 0 at Debug
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* Executing Context Stack level
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*/
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#define IX_NPEDL_ECS_DBG_CTXT_REG_0 0x0C
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/**
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* @def IX_NPEDL_ECS_DBG_CTXT_REG_1
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* @brief Execution Access register address for register 1 at Debug
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* Executing Context Stack level
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*/
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#define IX_NPEDL_ECS_DBG_CTXT_REG_1 0x0D
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/**
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* @def IX_NPEDL_ECS_DBG_CTXT_REG_2
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* @brief Execution Access register address for register 2 at Debug
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* Executing Context Stack level
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*/
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#define IX_NPEDL_ECS_DBG_CTXT_REG_2 0x0E
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/**
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* @def IX_NPEDL_ECS_INSTRUCT_REG
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* @brief Execution Access register address for NPE Instruction Register
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*/
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#define IX_NPEDL_ECS_INSTRUCT_REG 0x11
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/*
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* Execution Access register reset values
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*/
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/**
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* @def IX_NPEDL_ECS_BG_CTXT_REG_0_RESET
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* @brief Reset value for Execution Access Background ECS level register 0
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*/
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#define IX_NPEDL_ECS_BG_CTXT_REG_0_RESET 0xA0000000
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/**
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* @def IX_NPEDL_ECS_BG_CTXT_REG_1_RESET
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* @brief Reset value for Execution Access Background ECS level register 1
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*/
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#define IX_NPEDL_ECS_BG_CTXT_REG_1_RESET 0x01000000
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/**
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* @def IX_NPEDL_ECS_BG_CTXT_REG_2_RESET
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* @brief Reset value for Execution Access Background ECS level register 2
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*/
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#define IX_NPEDL_ECS_BG_CTXT_REG_2_RESET 0x00008000
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/**
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* @def IX_NPEDL_ECS_PRI_1_CTXT_REG_0_RESET
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* @brief Reset value for Execution Access Priority 1 ECS level register 0
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*/
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#define IX_NPEDL_ECS_PRI_1_CTXT_REG_0_RESET 0x20000080
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/**
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* @def IX_NPEDL_ECS_PRI_1_CTXT_REG_1_RESET
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* @brief Reset value for Execution Access Priority 1 ECS level register 1
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*/
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#define IX_NPEDL_ECS_PRI_1_CTXT_REG_1_RESET 0x01000000
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/**
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* @def IX_NPEDL_ECS_PRI_1_CTXT_REG_2_RESET
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* @brief Reset value for Execution Access Priority 1 ECS level register 2
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*/
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#define IX_NPEDL_ECS_PRI_1_CTXT_REG_2_RESET 0x00008000
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/**
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* @def IX_NPEDL_ECS_PRI_2_CTXT_REG_0_RESET
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* @brief Reset value for Execution Access Priority 2 ECS level register 0
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*/
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#define IX_NPEDL_ECS_PRI_2_CTXT_REG_0_RESET 0x20000080
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/**
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* @def IX_NPEDL_ECS_PRI_2_CTXT_REG_1_RESET
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* @brief Reset value for Execution Access Priority 2 ECS level register 1
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*/
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#define IX_NPEDL_ECS_PRI_2_CTXT_REG_1_RESET 0x01000000
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/**
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* @def IX_NPEDL_ECS_PRI_2_CTXT_REG_2_RESET
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* @brief Reset value for Execution Access Priority 2 ECS level register 2
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*/
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#define IX_NPEDL_ECS_PRI_2_CTXT_REG_2_RESET 0x00008000
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/**
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* @def IX_NPEDL_ECS_DBG_CTXT_REG_0_RESET
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* @brief Reset value for Execution Access Debug ECS level register 0
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*/
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#define IX_NPEDL_ECS_DBG_CTXT_REG_0_RESET 0x20000000
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/**
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* @def IX_NPEDL_ECS_DBG_CTXT_REG_1_RESET
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* @brief Reset value for Execution Access Debug ECS level register 1
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*/
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#define IX_NPEDL_ECS_DBG_CTXT_REG_1_RESET 0x00000000
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/**
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* @def IX_NPEDL_ECS_DBG_CTXT_REG_2_RESET
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* @brief Reset value for Execution Access Debug ECS level register 2
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*/
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#define IX_NPEDL_ECS_DBG_CTXT_REG_2_RESET 0x001E0000
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/**
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* @def IX_NPEDL_ECS_INSTRUCT_REG_RESET
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* @brief Reset value for Execution Access NPE Instruction Register
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*/
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#define IX_NPEDL_ECS_INSTRUCT_REG_RESET 0x1003C00F
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/*
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* masks used to read/write particular bits in Execution Access registers
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*/
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/**
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* @def IX_NPEDL_MASK_ECS_REG_0_ACTIVE
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* @brief Mask the A (Active) bit in Execution Access Register 0 of all ECS
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* levels
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*/
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#define IX_NPEDL_MASK_ECS_REG_0_ACTIVE 0x80000000
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/**
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* @def IX_NPEDL_MASK_ECS_REG_0_NEXTPC
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* @brief Mask the NextPC bits in Execution Access Register 0 of all ECS
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* levels (except Debug ECS level)
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*/
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#define IX_NPEDL_MASK_ECS_REG_0_NEXTPC 0x1FFF0000
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/**
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* @def IX_NPEDL_MASK_ECS_REG_0_LDUR
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* @brief Mask the LDUR bits in Execution Access Register 0 of all ECS levels
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*/
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#define IX_NPEDL_MASK_ECS_REG_0_LDUR 0x00000700
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/**
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* @def IX_NPEDL_MASK_ECS_REG_1_CCTXT
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* @brief Mask the NextPC bits in Execution Access Register 1 of all ECS levels
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*/
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#define IX_NPEDL_MASK_ECS_REG_1_CCTXT 0x000F0000
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/**
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* @def IX_NPEDL_MASK_ECS_REG_1_SELCTXT
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* @brief Mask the NextPC bits in Execution Access Register 1 of all ECS levels
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*/
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#define IX_NPEDL_MASK_ECS_REG_1_SELCTXT 0x0000000F
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/**
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* @def IX_NPEDL_MASK_ECS_DBG_REG_2_IF
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* @brief Mask the IF bit in Execution Access Register 2 of Debug ECS level
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*/
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#define IX_NPEDL_MASK_ECS_DBG_REG_2_IF 0x00100000
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/**
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* @def IX_NPEDL_MASK_ECS_DBG_REG_2_IE
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* @brief Mask the IE bit in Execution Access Register 2 of Debug ECS level
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*/
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#define IX_NPEDL_MASK_ECS_DBG_REG_2_IE 0x00080000
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/*
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* Bit-Offsets from LSB of particular bit-fields in Execution Access registers
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*/
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/**
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|
* @def IX_NPEDL_OFFSET_ECS_REG_0_NEXTPC
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* @brief LSB-offset of NextPC field in Execution Access Register 0 of all ECS
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|
* levels (except Debug ECS level)
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*/
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|
#define IX_NPEDL_OFFSET_ECS_REG_0_NEXTPC 16
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/**
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|
* @def IX_NPEDL_OFFSET_ECS_REG_0_LDUR
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* @brief LSB-offset of LDUR field in Execution Access Register 0 of all ECS
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|
* levels
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|
*/
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|
#define IX_NPEDL_OFFSET_ECS_REG_0_LDUR 8
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/**
|
|
* @def IX_NPEDL_OFFSET_ECS_REG_1_CCTXT
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* @brief LSB-offset of CCTXT field in Execution Access Register 1 of all ECS
|
|
* levels
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|
*/
|
|
#define IX_NPEDL_OFFSET_ECS_REG_1_CCTXT 16
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|
|
/**
|
|
* @def IX_NPEDL_OFFSET_ECS_REG_1_SELCTXT
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* @brief LSB-offset of SELCTXT field in Execution Access Register 1 of all ECS
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|
* levels
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*/
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|
#define IX_NPEDL_OFFSET_ECS_REG_1_SELCTXT 0
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|
|
|
|
/*
|
|
* NPE core & co-processor instruction templates to load into NPE Instruction
|
|
* Register, for read/write of NPE register file registers
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|
*/
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/**
|
|
* @def IX_NPEDL_INSTR_RD_REG_BYTE
|
|
* @brief NPE Instruction, used to read an 8-bit NPE internal logical register
|
|
* and return the value in the EXDATA register (aligned to MSB).
|
|
* NPE Assembler instruction: "mov8 d0, d0 &&& DBG_WrExec"
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|
*/
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|
#define IX_NPEDL_INSTR_RD_REG_BYTE 0x0FC00000
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|
|
/**
|
|
* @def IX_NPEDL_INSTR_RD_REG_SHORT
|
|
* @brief NPE Instruction, used to read a 16-bit NPE internal logical register
|
|
* and return the value in the EXDATA register (aligned to MSB).
|
|
* NPE Assembler instruction: "mov16 d0, d0 &&& DBG_WrExec"
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|
*/
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|
#define IX_NPEDL_INSTR_RD_REG_SHORT 0x0FC08010
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|
|
/**
|
|
* @def IX_NPEDL_INSTR_RD_REG_WORD
|
|
* @brief NPE Instruction, used to read a 16-bit NPE internal logical register
|
|
* and return the value in the EXDATA register.
|
|
* NPE Assembler instruction: "mov32 d0, d0 &&& DBG_WrExec"
|
|
*/
|
|
#define IX_NPEDL_INSTR_RD_REG_WORD 0x0FC08210
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|
|
/**
|
|
* @def IX_NPEDL_INSTR_WR_REG_BYTE
|
|
* @brief NPE Immediate-Mode Instruction, used to write an 8-bit NPE internal
|
|
* logical register.
|
|
* NPE Assembler instruction: "mov8 d0, #0"
|
|
*/
|
|
#define IX_NPEDL_INSTR_WR_REG_BYTE 0x00004000
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|
|
|
/**
|
|
* @def IX_NPEDL_INSTR_WR_REG_SHORT
|
|
* @brief NPE Immediate-Mode Instruction, used to write a 16-bit NPE internal
|
|
* logical register.
|
|
* NPE Assembler instruction: "mov16 d0, #0"
|
|
*/
|
|
#define IX_NPEDL_INSTR_WR_REG_SHORT 0x0000C000
|
|
|
|
/**
|
|
* @def IX_NPEDL_INSTR_RD_FIFO
|
|
* @brief NPE Immediate-Mode Instruction, used to write a 16-bit NPE internal
|
|
* logical register.
|
|
* NPE Assembler instruction: "cprd32 d0 &&& DBG_RdInFIFO"
|
|
*/
|
|
#define IX_NPEDL_INSTR_RD_FIFO 0x0F888220
|
|
|
|
/**
|
|
* @def IX_NPEDL_INSTR_RESET_MBOX
|
|
* @brief NPE Instruction, used to reset Mailbox (MBST) register
|
|
* NPE Assembler instruction: "mov32 d0, d0 &&& DBG_ClearM"
|
|
*/
|
|
#define IX_NPEDL_INSTR_RESET_MBOX 0x0FAC8210
|
|
|
|
|
|
/*
|
|
* Bit-offsets from LSB, of particular bit-fields in an NPE instruction
|
|
*/
|
|
|
|
/**
|
|
* @def IX_NPEDL_OFFSET_INSTR_SRC
|
|
* @brief LSB-offset to SRC (source operand) field of an NPE Instruction
|
|
*/
|
|
#define IX_NPEDL_OFFSET_INSTR_SRC 4
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|
|
|
/**
|
|
* @def IX_NPEDL_OFFSET_INSTR_DEST
|
|
* @brief LSB-offset to DEST (destination operand) field of an NPE Instruction
|
|
*/
|
|
#define IX_NPEDL_OFFSET_INSTR_DEST 9
|
|
|
|
/**
|
|
* @def IX_NPEDL_OFFSET_INSTR_COPROC
|
|
* @brief LSB-offset to COPROC (coprocessor instruction) field of an NPE
|
|
* Instruction
|
|
*/
|
|
#define IX_NPEDL_OFFSET_INSTR_COPROC 18
|
|
|
|
|
|
/*
|
|
* masks used to read/write particular bits of an NPE Instruction
|
|
*/
|
|
|
|
/**
|
|
* @def IX_NPEDL_MASK_IMMED_INSTR_SRC_DATA
|
|
* @brief Mask the bits of 16-bit data value (least-sig 5 bits) to be used in
|
|
* SRC field of immediate-mode NPE instruction
|
|
*/
|
|
#define IX_NPEDL_MASK_IMMED_INSTR_SRC_DATA 0x1F
|
|
|
|
/**
|
|
* @def IX_NPEDL_MASK_IMMED_INSTR_COPROC_DATA
|
|
* @brief Mask the bits of 16-bit data value (most-sig 11 bits) to be used in
|
|
* COPROC field of immediate-mode NPE instruction
|
|
*/
|
|
#define IX_NPEDL_MASK_IMMED_INSTR_COPROC_DATA 0xFFE0
|
|
|
|
/**
|
|
* @def IX_NPEDL_OFFSET_IMMED_INSTR_COPROC_DATA
|
|
* @brief LSB offset of the bit-field of 16-bit data value (most-sig 11 bits)
|
|
* to be used in COPROC field of immediate-mode NPE instruction
|
|
*/
|
|
#define IX_NPEDL_OFFSET_IMMED_INSTR_COPROC_DATA 5
|
|
|
|
/**
|
|
* @def IX_NPEDL_DISPLACE_IMMED_INSTR_COPROC_DATA
|
|
* @brief Number of left-shifts required to align most-sig 11 bits of 16-bit
|
|
* data value into COPROC field of immediate-mode NPE instruction
|
|
*/
|
|
#define IX_NPEDL_DISPLACE_IMMED_INSTR_COPROC_DATA \
|
|
(IX_NPEDL_OFFSET_INSTR_COPROC - IX_NPEDL_OFFSET_IMMED_INSTR_COPROC_DATA)
|
|
|
|
/**
|
|
* @def IX_NPEDL_WR_INSTR_LDUR
|
|
* @brief LDUR value used with immediate-mode NPE Instructions by the NpeDl
|
|
* for writing to NPE internal logical registers
|
|
*/
|
|
#define IX_NPEDL_WR_INSTR_LDUR 1
|
|
|
|
/**
|
|
* @def IX_NPEDL_RD_INSTR_LDUR
|
|
* @brief LDUR value used with NON-immediate-mode NPE Instructions by the NpeDl
|
|
* for reading from NPE internal logical registers
|
|
*/
|
|
#define IX_NPEDL_RD_INSTR_LDUR 0
|
|
|
|
|
|
/**
|
|
* @enum IxNpeDlCtxtRegNum
|
|
* @brief Numeric values to identify the NPE internal Context Store registers
|
|
*/
|
|
typedef enum
|
|
{
|
|
IX_NPEDL_CTXT_REG_STEVT = 0, /**< identifies STEVT */
|
|
IX_NPEDL_CTXT_REG_STARTPC, /**< identifies STARTPC */
|
|
IX_NPEDL_CTXT_REG_REGMAP, /**< identifies REGMAP */
|
|
IX_NPEDL_CTXT_REG_CINDEX, /**< identifies CINDEX */
|
|
IX_NPEDL_CTXT_REG_MAX /**< Total number of Context Store registers */
|
|
} IxNpeDlCtxtRegNum;
|
|
|
|
|
|
/*
|
|
* NPE Context Store register logical addresses
|
|
*/
|
|
|
|
/**
|
|
* @def IX_NPEDL_CTXT_REG_ADDR_STEVT
|
|
* @brief Logical address of STEVT NPE internal Context Store register
|
|
*/
|
|
#define IX_NPEDL_CTXT_REG_ADDR_STEVT 0x0000001B
|
|
|
|
/**
|
|
* @def IX_NPEDL_CTXT_REG_ADDR_STARTPC
|
|
* @brief Logical address of STARTPC NPE internal Context Store register
|
|
*/
|
|
#define IX_NPEDL_CTXT_REG_ADDR_STARTPC 0x0000001C
|
|
|
|
/**
|
|
* @def IX_NPEDL_CTXT_REG_ADDR_REGMAP
|
|
* @brief Logical address of REGMAP NPE internal Context Store register
|
|
*/
|
|
#define IX_NPEDL_CTXT_REG_ADDR_REGMAP 0x0000001E
|
|
|
|
/**
|
|
* @def IX_NPEDL_CTXT_REG_ADDR_CINDEX
|
|
* @brief Logical address of CINDEX NPE internal Context Store register
|
|
*/
|
|
#define IX_NPEDL_CTXT_REG_ADDR_CINDEX 0x0000001F
|
|
|
|
|
|
/*
|
|
* NPE Context Store register reset values
|
|
*/
|
|
|
|
/**
|
|
* @def IX_NPEDL_CTXT_REG_RESET_STEVT
|
|
* @brief Reset value of STEVT NPE internal Context Store register
|
|
* (STEVT = off, 0x80)
|
|
*/
|
|
#define IX_NPEDL_CTXT_REG_RESET_STEVT 0x80
|
|
|
|
/**
|
|
* @def IX_NPEDL_CTXT_REG_RESET_STARTPC
|
|
* @brief Reset value of STARTPC NPE internal Context Store register
|
|
* (STARTPC = 0x0000)
|
|
*/
|
|
#define IX_NPEDL_CTXT_REG_RESET_STARTPC 0x0000
|
|
|
|
/**
|
|
* @def IX_NPEDL_CTXT_REG_RESET_REGMAP
|
|
* @brief Reset value of REGMAP NPE internal Context Store register
|
|
* (REGMAP = d0->p0, d8->p2, d16->p4)
|
|
*/
|
|
#define IX_NPEDL_CTXT_REG_RESET_REGMAP 0x0820
|
|
|
|
/**
|
|
* @def IX_NPEDL_CTXT_REG_RESET_CINDEX
|
|
* @brief Reset value of CINDEX NPE internal Context Store register
|
|
* (CINDEX = 0)
|
|
*/
|
|
#define IX_NPEDL_CTXT_REG_RESET_CINDEX 0x00
|
|
|
|
|
|
/*
|
|
* numeric range of context levels available on an NPE
|
|
*/
|
|
|
|
/**
|
|
* @def IX_NPEDL_CTXT_NUM_MIN
|
|
* @brief Lowest NPE Context number in range
|
|
*/
|
|
#define IX_NPEDL_CTXT_NUM_MIN 0
|
|
|
|
/**
|
|
* @def IX_NPEDL_CTXT_NUM_MAX
|
|
* @brief Highest NPE Context number in range
|
|
*/
|
|
#define IX_NPEDL_CTXT_NUM_MAX 15
|
|
|
|
|
|
/*
|
|
* Physical NPE internal registers
|
|
*/
|
|
|
|
/**
|
|
* @def IX_NPEDL_TOTAL_NUM_PHYS_REG
|
|
* @brief Number of Physical registers currently supported
|
|
* Initial NPE implementations will have a 32-word register file.
|
|
* Later implementations may have a 64-word register file.
|
|
*/
|
|
#define IX_NPEDL_TOTAL_NUM_PHYS_REG 32
|
|
|
|
/**
|
|
* @def IX_NPEDL_OFFSET_PHYS_REG_ADDR_REGMAP
|
|
* @brief LSB-offset of Regmap number in Physical NPE register address, used
|
|
* for Physical To Logical register address mapping in the NPE
|
|
*/
|
|
#define IX_NPEDL_OFFSET_PHYS_REG_ADDR_REGMAP 1
|
|
|
|
/**
|
|
* @def IX_NPEDL_MASK_PHYS_REG_ADDR_LOGICAL_ADDR
|
|
* @brief Mask to extract a logical NPE register address from a physical
|
|
* register address, used for Physical To Logical address mapping
|
|
*/
|
|
#define IX_NPEDL_MASK_PHYS_REG_ADDR_LOGICAL_ADDR 0x1
|
|
|
|
#endif /* IXNPEDLNPEMGRECREGISTERS_P_H */
|