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![Marek Vasut](/assets/img/avatar_default.png)
Signed-off-by: Marek Vasut <marex@denx.de> Cc: Bryan Hundven <bryanhundven@gmail.com> Cc: Michael Schwingen <rincewind@discworld.dascon.de> Cc: Wolfgang Denk <wd@denx.de> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: U-Boot DM <u-boot-dm@lists.denx.de> Cc: Joe Hershberger <joe.hershberger@ni.com>
783 lines
22 KiB
C
783 lines
22 KiB
C
#ifndef __doxygen_HIDE /* This file is not part of the API */
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/**
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* @file IxNpeA.h
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*
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* @date 22-Mar-2002
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*
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* @brief Header file for the IXP400 ATM NPE API
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*
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*
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* @par
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* IXP400 SW Release version 2.0
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*
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* -- Copyright Notice --
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*
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* @par
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* Copyright 2001-2005, Intel Corporation.
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* All rights reserved.
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*
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* @par
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of the Intel Corporation nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* @par
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* @par
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* -- End of Copyright Notice --
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*/
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/**
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* @defgroup IxNpeA IXP400 NPE-A (IxNpeA) API
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*
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* @brief The Public API for the IXP400 NPE-A
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*
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* @{
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*/
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#ifndef IX_NPE_A_H
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#define IX_NPE_A_H
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#include "IxQMgr.h"
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#include "IxOsal.h"
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#include "IxQueueAssignments.h"
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/* General Message Ids */
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/* ATM Message Ids */
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/**
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* @def IX_NPE_A_MSSG_ATM_UTOPIA_CONFIG_WRITE
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*
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* @brief ATM Message ID command to write the data to the offset in the
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* Utopia Configuration Table
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*/
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#define IX_NPE_A_MSSG_ATM_UTOPIA_CONFIG_WRITE 0x20
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/**
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* @def IX_NPE_A_MSSG_ATM_UTOPIA_CONFIG_LOAD
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*
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* @brief ATM Message ID command triggers the NPE to copy the Utopia
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* Configuration Table to the Utopia coprocessor
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*/
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#define IX_NPE_A_MSSG_ATM_UTOPIA_CONFIG_LOAD 0x21
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/**
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* @def IX_NPE_A_MSSG_ATM_UTOPIA_STATUS_UPLOAD
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*
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* @brief ATM Message ID command triggers the NPE to read-back the Utopia
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* status registers and update the Utopia Status Table.
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*/
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#define IX_NPE_A_MSSG_ATM_UTOPIA_STATUS_UPLOAD 0x22
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/**
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* @def IX_NPE_A_MSSG_ATM_UTOPIA_STATUS_READ
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*
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* @brief ATM Message ID command to read the Utopia Status Table at the
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* specified offset.
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*/
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#define IX_NPE_A_MSSG_ATM_UTOPIA_STATUS_READ 0x23
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/**
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* @def IX_NPE_A_MSSG_ATM_TX_ENABLE
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*
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* @brief ATM Message ID command triggers the NPE to re-enable processing
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* of any entries on the TxVcQ for this port.
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*
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* This command will be ignored for a port already enabled
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*/
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#define IX_NPE_A_MSSG_ATM_TX_ENABLE 0x25
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/**
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* @def IX_NPE_A_MSSG_ATM_TX_DISABLE
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*
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* @brief ATM Message ID command triggers the NPE to disable processing on
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* this port
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*
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* This command will be ignored for a port already disabled
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*/
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#define IX_NPE_A_MSSG_ATM_TX_DISABLE 0x26
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/**
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* @def IX_NPE_A_MSSG_ATM_RX_ENABLE
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*
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* @brief ATM Message ID command triggers the NPE to process any received
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* cells for this VC according to the VC Lookup Table.
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*
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* Re-issuing this command with different contents for a VC that is not
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* disabled will cause unpredictable behavior.
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*/
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#define IX_NPE_A_MSSG_ATM_RX_ENABLE 0x27
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/**
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* @def IX_NPE_A_MSSG_ATM_RX_DISABLE
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*
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* @brief ATM Message ID command triggers the NPE to disable processing for
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* this VC.
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*
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* This command will be ignored for a VC already disabled
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*/
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#define IX_NPE_A_MSSG_ATM_RX_DISABLE 0x28
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/**
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* @def IX_NPE_A_MSSG_ATM_STATUS_READ
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*
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* @brief ATM Message ID command to read the ATM status. The data is returned via
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* a response message
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*/
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#define IX_NPE_A_MSSG_ATM_STATUS_READ 0x29
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/*--------------------------------------------------------------------------
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* HSS Message IDs
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*--------------------------------------------------------------------------*/
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/**
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* @def IX_NPE_A_MSSG_HSS_PORT_CONFIG_WRITE
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*
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* @brief HSS Message ID command writes the ConfigWord value to the location
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* in the HSS_CONFIG_TABLE specified by offset for HSS port hPort.
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*/
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#define IX_NPE_A_MSSG_HSS_PORT_CONFIG_WRITE 0x40
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/**
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* @def IX_NPE_A_MSSG_HSS_PORT_CONFIG_LOAD
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*
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* @brief HSS Message ID command triggers the NPE to copy the contents of the
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* HSS Configuration Table to the appropriate configuration registers in the
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* HSS coprocessor for the port specified by hPort.
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*/
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#define IX_NPE_A_MSSG_HSS_PORT_CONFIG_LOAD 0x41
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/**
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* @def IX_NPE_A_MSSG_HSS_PORT_ERROR_READ
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*
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* @brief HSS Message ID command triggers the NPE to return an HssErrorReadResponse
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* message for HSS port hPort.
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*/
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#define IX_NPE_A_MSSG_HSS_PORT_ERROR_READ 0x42
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/**
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* @def IX_NPE_A_MSSG_HSS_CHAN_FLOW_ENABLE
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*
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* @brief HSS Message ID command triggers the NPE to reset internal status and
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* enable the HssChannelized operation on the HSS port specified by hPort.
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*/
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#define IX_NPE_A_MSSG_HSS_CHAN_FLOW_ENABLE 0x43
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/**
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* @def IX_NPE_A_MSSG_HSS_CHAN_FLOW_DISABLE
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*
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* @brief HSS Message ID command triggers the NPE to disable the HssChannelized
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* operation on the HSS port specified by hPort.
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*/
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#define IX_NPE_A_MSSG_HSS_CHAN_FLOW_DISABLE 0x44
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/**
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* @def IX_NPE_A_MSSG_HSS_CHAN_IDLE_PATTERN_WRITE
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*
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* @brief HSS Message ID command writes the HSSnC_IDLE_PATTERN value for HSS
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* port hPort. (n=hPort)
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*/
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#define IX_NPE_A_MSSG_HSS_CHAN_IDLE_PATTERN_WRITE 0x45
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/**
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* @def IX_NPE_A_MSSG_HSS_CHAN_NUM_CHANS_WRITE
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*
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* @brief HSS Message ID command writes the HSSnC_NUM_CHANNELS value for HSS
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* port hPort. (n=hPort)
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*/
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#define IX_NPE_A_MSSG_HSS_CHAN_NUM_CHANS_WRITE 0x46
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/**
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* @def IX_NPE_A_MSSG_HSS_CHAN_RX_BUF_ADDR_WRITE
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*
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* @brief HSS Message ID command writes the HSSnC_RX_BUF_ADDR value for HSS
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* port hPort. (n=hPort)
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*/
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#define IX_NPE_A_MSSG_HSS_CHAN_RX_BUF_ADDR_WRITE 0x47
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/**
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* @def IX_NPE_A_MSSG_HSS_CHAN_RX_BUF_CFG_WRITE
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*
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* @brief HSS Message ID command writes the HSSnC_RX_BUF_SIZEB and
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* HSSnC_RX_TRIG_PERIOD values for HSS port hPort. (n=hPort)
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*/
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#define IX_NPE_A_MSSG_HSS_CHAN_RX_BUF_CFG_WRITE 0x48
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/**
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* @def IX_NPE_A_MSSG_HSS_CHAN_TX_BLK_CFG_WRITE
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*
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* @brief HSS Message ID command writes the HSSnC_TX_BLK1_SIZEB,
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* HSSnC_TX_BLK1_SIZEW, HSSnC_TX_BLK2_SIZEB, and HSSnC_TX_BLK2_SIZEW values
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* for HSS port hPort. (n=hPort)
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*/
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#define IX_NPE_A_MSSG_HSS_CHAN_TX_BLK_CFG_WRITE 0x49
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/**
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* @def IX_NPE_A_MSSG_HSS_CHAN_TX_BUF_ADDR_WRITE
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* @brief HSS Message ID command writes the HSSnC_TX_BUF_ADDR value for HSS
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* port hPort. (n=hPort)
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*/
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#define IX_NPE_A_MSSG_HSS_CHAN_TX_BUF_ADDR_WRITE 0x4A
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/**
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* @def IX_NPE_A_MSSG_HSS_CHAN_TX_BUF_SIZE_WRITE
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*
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* @brief HSS Message ID command writes the HSSnC_TX_BUF_SIZEN value for HSS
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* port hPort. (n=hPort)
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*/
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#define IX_NPE_A_MSSG_HSS_CHAN_TX_BUF_SIZE_WRITE 0x4B
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/**
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* @def IX_NPE_A_MSSG_HSS_PKT_PIPE_FLOW_ENABLE
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*
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* @brief HSS Message ID command triggers the NPE to reset internal status and
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* enable the HssPacketized operation for the flow specified by pPipe on
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* the HSS port specified by hPort.
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*/
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#define IX_NPE_A_MSSG_HSS_PKT_PIPE_FLOW_ENABLE 0x50
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/**
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* @def IX_NPE_A_MSSG_HSS_PKT_PIPE_FLOW_DISABLE
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* @brief HSS Message ID command triggers the NPE to disable the HssPacketized
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* operation for the flow specified by pPipe on the HSS port specified by hPort.
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*/
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#define IX_NPE_A_MSSG_HSS_PKT_PIPE_FLOW_DISABLE 0x51
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/**
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* @def IX_NPE_A_MSSG_HSS_PKT_NUM_PIPES_WRITE
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* @brief HSS Message ID command writes the HSSnP_NUM_PIPES value for HSS
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* port hPort.(n=hPort)
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*/
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#define IX_NPE_A_MSSG_HSS_PKT_NUM_PIPES_WRITE 0x52
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/**
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* @def IX_NPE_A_MSSG_HSS_PKT_PIPE_FIFO_SIZEW_WRITE
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*
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* @brief HSS Message ID command writes the HSSnP_PIPEp_FIFOSIZEW value for
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* packet-pipe pPipe on HSS port hPort. (n=hPort, p=pPipe)
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*/
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#define IX_NPE_A_MSSG_HSS_PKT_PIPE_FIFO_SIZEW_WRITE 0x53
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/**
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* @def IX_NPE_A_MSSG_HSS_PKT_PIPE_HDLC_CFG_WRITE
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*
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* @brief HSS Message ID command writes the HSSnP_PIPEp_HDLC_RXCFG and
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* HSSnP_PIPEp_HDLC_TXCFG values for packet-pipe pPipe on HSS port hPort.
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* (n=hPort, p=pPipe)
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*/
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#define IX_NPE_A_MSSG_HSS_PKT_PIPE_HDLC_CFG_WRITE 0x54
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/**
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* @def IX_NPE_A_MSSG_HSS_PKT_PIPE_IDLE_PATTERN_WRITE
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*
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* @brief HSS Message ID command writes the HSSnP_PIPEp_IDLE_PATTERN value
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* for packet-pipe pPipe on HSS port hPort. (n=hPort, p=pPipe)
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*/
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#define IX_NPE_A_MSSG_HSS_PKT_PIPE_IDLE_PATTERN_WRITE 0x55
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/**
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* @def IX_NPE_A_MSSG_HSS_PKT_PIPE_RX_SIZE_WRITE
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*
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* @brief HSS Message ID command writes the HSSnP_PIPEp_RXSIZEB value for
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* packet-pipe pPipe on HSS port hPort. (n=hPort, p=pPipe)
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*/
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#define IX_NPE_A_MSSG_HSS_PKT_PIPE_RX_SIZE_WRITE 0x56
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/**
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* @def IX_NPE_A_MSSG_HSS_PKT_PIPE_MODE_WRITE
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*
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* @brief HSS Message ID command writes the HSSnP_PIPEp_MODE value for
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* packet-pipe pPipe on HSS port hPort. (n=hPort, p=pPipe)
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*/
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#define IX_NPE_A_MSSG_HSS_PKT_PIPE_MODE_WRITE 0x57
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/* Queue Entry Masks */
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/*--------------------------------------------------------------------------
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* ATM Descriptor Structure offsets
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*--------------------------------------------------------------------------*/
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/**
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* @def IX_NPE_A_RXDESCRIPTOR_STATUS_OFFSET
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*
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* @brief ATM Descriptor structure offset for Receive Descriptor Status field
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*
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* It is used for descriptor error reporting.
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*/
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#define IX_NPE_A_RXDESCRIPTOR_STATUS_OFFSET 0
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/**
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* @def IX_NPE_A_RXDESCRIPTOR_VCID_OFFSET
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*
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* @brief ATM Descriptor structure offset for Receive Descriptor VC ID field
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*
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* It is used to hold an identifier number for this VC
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*/
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#define IX_NPE_A_RXDESCRIPTOR_VCID_OFFSET 1
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/**
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* @def IX_NPE_A_RXDESCRIPTOR_CURRMBUFSIZE_OFFSET
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*
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* @brief ATM Descriptor structure offset for Receive Descriptor Current Mbuf
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* Size field
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*
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* Number of bytes the current mbuf data buffer can hold
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*/
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#define IX_NPE_A_RXDESCRIPTOR_CURRMBUFSIZE_OFFSET 2
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/**
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* @def IX_NPE_A_RXDESCRIPTOR_ATMHEADER_OFFSET
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*
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* @brief ATM Descriptor structure offset for Receive Descriptor ATM Header
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*/
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#define IX_NPE_A_RXDESCRIPTOR_ATMHEADER_OFFSET 4
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/**
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* @def IX_NPE_A_RXDESCRIPTOR_CURRMBUFLEN_OFFSET
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*
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* @brief ATM Descriptor structure offset for Receive Descriptor Current MBuf length
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*
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*
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* RX - Initialized to zero. The NPE updates this field as each cell is received and
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* zeroes it with every new mbuf for chaining. Will not be bigger than currBbufSize.
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*/
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#define IX_NPE_A_RXDESCRIPTOR_CURRMBUFLEN_OFFSET 12
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/**
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* @def IX_NPE_A_RXDESCRIPTOR_TIMELIMIT__OFFSET
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*
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* @brief ATM Descriptor structure offset for Receive Descriptor Time Limit field
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*
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* Contains the Payload Reassembly Time Limit (used for aal0_xx only)
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*/
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#define IX_NPE_A_RXDESCRIPTOR_TIMELIMIT_OFFSET 14
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/**
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* @def IX_NPE_A_RXDESCRIPTOR_PCURRMBUFF_OFFSET
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*
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* @brief ATM Descriptor structure offset for Receive Descriptor Current MBuf Pointer
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*
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* The current mbuf pointer of a chain of mbufs.
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*/
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#define IX_NPE_A_RXDESCRIPTOR_PCURRMBUFF_OFFSET 20
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/**
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* @def IX_NPE_A_RXDESCRIPTOR_PCURRMBUFDATA_OFFSET
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*
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* @brief ATM Descriptor structure offset for Receive Descriptor Current MBuf Pointer
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*
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* Pointer to the next byte to be read or next free location to be written.
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*/
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#define IX_NPE_A_RXDESCRIPTOR_PCURRMBUFDATA_OFFSET 24
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/**
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* @def IX_NPE_A_RXDESCRIPTOR_PNEXTMBUF_OFFSET
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*
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* @brief ATM Descriptor structure offset for Receive Descriptor Next MBuf Pointer
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*
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* Pointer to the next MBuf in a chain of MBufs.
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*/
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#define IX_NPE_A_RXDESCRIPTOR_PNEXTMBUF_OFFSET 28
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/**
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* @def IX_NPE_A_RXDESCRIPTOR_TOTALLENGTH_OFFSET
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*
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* @brief ATM Descriptor structure offset for Receive Descriptor Total Length
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*
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* Total number of bytes written to the chain of MBufs by the NPE
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*/
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#define IX_NPE_A_RXDESCRIPTOR_TOTALLENGTH_OFFSET 32
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/**
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* @def IX_NPE_A_RXDESCRIPTOR_AAL5CRCRESIDUE_OFFSET
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*
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* @brief ATM Descriptor structure offset for Receive Descriptor AAL5 CRC Residue
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*
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* Current CRC value for a PDU
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*/
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#define IX_NPE_A_RXDESCRIPTOR_AAL5CRCRESIDUE_OFFSET 36
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/**
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* @def IX_NPE_A_RXDESCRIPTOR_SIZE
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*
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* @brief ATM Descriptor structure offset for Receive Descriptor Size
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*
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* The size of the Receive descriptor
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*/
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#define IX_NPE_A_RXDESCRIPTOR_SIZE 40
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/**
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* @def IX_NPE_A_TXDESCRIPTOR_PORT_OFFSET
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*
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* @brief ATM Descriptor structure offset for Transmit Descriptor Port
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*
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* Port identifier.
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*/
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#define IX_NPE_A_TXDESCRIPTOR_PORT_OFFSET 0
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/**
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* @def IX_NPE_A_TXDESCRIPTOR_RSVD_OFFSET
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*
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* @brief ATM Descriptor structure offset for Transmit Descriptor RSVD
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*/
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#define IX_NPE_A_TXDESCRIPTOR_RSVD_OFFSET 1
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/**
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* @def IX_NPE_A_TXDESCRIPTOR_CURRMBUFLEN_OFFSET
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*
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* @brief ATM Descriptor structure offset for Transmit Descriptor Current MBuf Length
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*
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* TX - Initialized by the XScale to the number of bytes in the current MBuf data buffer.
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* The NPE decrements this field for every transmitted cell. Thus, when the NPE writes a
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* descriptor the TxDone queue, this field will equal zero.
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*/
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#define IX_NPE_A_TXDESCRIPTOR_CURRMBUFLEN_OFFSET 2
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/**
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* @def IX_NPE_A_TXDESCRIPTOR_ATMHEADER_OFFSET
|
|
* @brief ATM Descriptor structure offset for Transmit Descriptor ATM Header
|
|
*/
|
|
#define IX_NPE_A_TXDESCRIPTOR_ATMHEADER_OFFSET 4
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|
|
|
/**
|
|
* @def IX_NPE_A_TXDESCRIPTOR_PCURRMBUFF_OFFSET
|
|
*
|
|
* @brief ATM Descriptor structure offset for Transmit Descriptor Pointer to the current MBuf chain
|
|
*/
|
|
#define IX_NPE_A_TXDESCRIPTOR_PCURRMBUFF_OFFSET 8
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|
|
|
/**
|
|
* @def IX_NPE_A_TXDESCRIPTOR_PCURRMBUFDATA_OFFSET
|
|
*
|
|
* @brief ATM Descriptor structure offset for Transmit Descriptor Pointer to the current MBuf Data
|
|
*
|
|
* Pointer to the next byte to be read or next free location to be written.
|
|
*/
|
|
#define IX_NPE_A_TXDESCRIPTOR_PCURRMBUFDATA_OFFSET 12
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|
|
|
/**
|
|
* @def IX_NPE_A_TXDESCRIPTOR_PNEXTMBUF_OFFSET
|
|
*
|
|
* @brief ATM Descriptor structure offset for Transmit Descriptor Pointer to the Next MBuf chain
|
|
*/
|
|
#define IX_NPE_A_TXDESCRIPTOR_PNEXTMBUF_OFFSET 16
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|
|
|
/**
|
|
* @def IX_NPE_A_TXDESCRIPTOR_TOTALLENGTH_OFFSET
|
|
*
|
|
* @brief ATM Descriptor structure offset for Transmit Descriptor Total Length
|
|
*
|
|
* Total number of bytes written to the chain of MBufs by the NPE
|
|
*/
|
|
#define IX_NPE_A_TXDESCRIPTOR_TOTALLENGTH_OFFSET 20
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|
|
|
/**
|
|
* @def IX_NPE_A_TXDESCRIPTOR_AAL5CRCRESIDUE_OFFSET
|
|
*
|
|
* @brief ATM Descriptor structure offset for Transmit Descriptor AAL5 CRC Residue
|
|
*
|
|
* Current CRC value for a PDU
|
|
*/
|
|
#define IX_NPE_A_TXDESCRIPTOR_AAL5CRCRESIDUE_OFFSET 24
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|
|
|
/**
|
|
* @def IX_NPE_A_TXDESCRIPTOR_SIZE
|
|
*
|
|
* @brief ATM Descriptor structure offset for Transmit Descriptor Size
|
|
*/
|
|
#define IX_NPE_A_TXDESCRIPTOR_SIZE 28
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|
|
|
/**
|
|
* @def IX_NPE_A_CHAIN_DESC_COUNT_MAX
|
|
*
|
|
* @brief Maximum number of chained MBufs that can be chained together
|
|
*/
|
|
#define IX_NPE_A_CHAIN_DESC_COUNT_MAX 256
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|
|
|
/*
|
|
* Definition of the ATM cell header
|
|
*
|
|
* This would most conviently be defined as the bit field shown below.
|
|
* Endian portability prevents this, therefore a set of macros
|
|
* are defined to access the fields within the cell header assumed to
|
|
* be passed as a UINT32.
|
|
*
|
|
* Changes to field sizes or orders must be reflected in the offset
|
|
* definitions above.
|
|
*
|
|
* typedef struct
|
|
* {
|
|
* unsigned int gfc:4;
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|
* unsigned int vpi:8;
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|
* unsigned int vci:16;
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|
* unsigned int pti:3;
|
|
* unsigned int clp:1;
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|
* } IxNpeA_AtmCellHeader;
|
|
*
|
|
*/
|
|
|
|
/** Mask to acess GFC */
|
|
#define GFC_MASK 0xf0000000
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|
|
|
/** return GFC from ATM cell header */
|
|
#define IX_NPE_A_ATMCELLHEADER_GFC_GET( header ) \
|
|
(((header) & GFC_MASK) >> 28)
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|
|
|
/** set GFC into ATM cell header */
|
|
#define IX_NPE_A_ATMCELLHEADER_GFC_SET( header,gfc ) \
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|
do { \
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|
(header) &= ~GFC_MASK; \
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|
(header) |= (((gfc) << 28) & GFC_MASK); \
|
|
} while(0)
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|
|
|
/** Mask to acess VPI */
|
|
#define VPI_MASK 0x0ff00000
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|
|
|
/** return VPI from ATM cell header */
|
|
#define IX_NPE_A_ATMCELLHEADER_VPI_GET( header ) \
|
|
(((header) & VPI_MASK) >> 20)
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|
|
|
/** set VPI into ATM cell header */
|
|
#define IX_NPE_A_ATMCELLHEADER_VPI_SET( header, vpi ) \
|
|
do { \
|
|
(header) &= ~VPI_MASK; \
|
|
(header) |= (((vpi) << 20) & VPI_MASK); \
|
|
} while(0)
|
|
|
|
/** Mask to acess VCI */
|
|
#define VCI_MASK 0x000ffff0
|
|
|
|
/** return VCI from ATM cell header */
|
|
#define IX_NPE_A_ATMCELLHEADER_VCI_GET( header ) \
|
|
(((header) & VCI_MASK) >> 4)
|
|
|
|
/** set VCI into ATM cell header */
|
|
#define IX_NPE_A_ATMCELLHEADER_VCI_SET( header, vci ) \
|
|
do { \
|
|
(header) &= ~VCI_MASK; \
|
|
(header) |= (((vci) << 4) & VCI_MASK); \
|
|
} while(0)
|
|
|
|
/** Mask to acess PTI */
|
|
#define PTI_MASK 0x0000000e
|
|
|
|
/** return PTI from ATM cell header */
|
|
#define IX_NPE_A_ATMCELLHEADER_PTI_GET( header ) \
|
|
(((header) & PTI_MASK) >> 1)
|
|
|
|
/** set PTI into ATM cell header */
|
|
#define IX_NPE_A_ATMCELLHEADER_PTI_SET( header, pti ) \
|
|
do { \
|
|
(header) &= ~PTI_MASK; \
|
|
(header) |= (((pti) << 1) & PTI_MASK); \
|
|
} while(0)
|
|
|
|
/** Mask to acess CLP */
|
|
#define CLP_MASK 0x00000001
|
|
|
|
/** return CLP from ATM cell header */
|
|
#define IX_NPE_A_ATMCELLHEADER_CLP_GET( header ) \
|
|
((header) & CLP_MASK)
|
|
|
|
/** set CLP into ATM cell header */
|
|
#define IX_NPE_A_ATMCELLHEADER_CLP_SET( header, clp ) \
|
|
do { \
|
|
(header) &= ~CLP_MASK; \
|
|
(header) |= ((clp) & CLP_MASK); \
|
|
} while(0)
|
|
|
|
|
|
/*
|
|
* Definition of the Rx bitfield
|
|
*
|
|
* This would most conviently be defined as the bit field shown below.
|
|
* Endian portability prevents this, therefore a set of macros
|
|
* are defined to access the fields within the rxBitfield assumed to
|
|
* be passed as a UINT32.
|
|
*
|
|
* Changes to field sizes or orders must be reflected in the offset
|
|
* definitions above.
|
|
*
|
|
* Rx bitfield
|
|
* struct
|
|
* { IX_NPEA_RXBITFIELD(
|
|
* unsigned int status:1,
|
|
* unsigned int port:7,
|
|
* unsigned int vcId:8,
|
|
* unsigned int currMbufSize:16);
|
|
* } rxBitField;
|
|
*
|
|
*/
|
|
|
|
/** Mask to acess the rxBitField status */
|
|
#define STATUS_MASK 0x80000000
|
|
|
|
/** return the rxBitField status */
|
|
#define IX_NPE_A_RXBITFIELD_STATUS_GET( rxbitfield ) \
|
|
(((rxbitfield) & STATUS_MASK) >> 31)
|
|
|
|
/** set the rxBitField status */
|
|
#define IX_NPE_A_RXBITFIELD_STATUS_SET( rxbitfield, status ) \
|
|
do { \
|
|
(rxbitfield) &= ~STATUS_MASK; \
|
|
(rxbitfield) |= (((status) << 31) & STATUS_MASK); \
|
|
} while(0)
|
|
|
|
/** Mask to acess the rxBitField port */
|
|
#define PORT_MASK 0x7f000000
|
|
|
|
/** return the rxBitField port */
|
|
#define IX_NPE_A_RXBITFIELD_PORT_GET( rxbitfield ) \
|
|
(((rxbitfield) & PORT_MASK) >> 24)
|
|
|
|
/** set the rxBitField port */
|
|
#define IX_NPE_A_RXBITFIELD_PORT_SET( rxbitfield, port ) \
|
|
do { \
|
|
(rxbitfield) &= ~PORT_MASK; \
|
|
(rxbitfield) |= (((port) << 24) & PORT_MASK); \
|
|
} while(0)
|
|
|
|
/** Mask to acess the rxBitField vcId */
|
|
#define VCID_MASK 0x00ff0000
|
|
|
|
/** return the rxBitField vcId */
|
|
#define IX_NPE_A_RXBITFIELD_VCID_GET( rxbitfield ) \
|
|
(((rxbitfield) & VCID_MASK) >> 16)
|
|
|
|
/** set the rxBitField vcId */
|
|
#define IX_NPE_A_RXBITFIELD_VCID_SET( rxbitfield, vcid ) \
|
|
do { \
|
|
(rxbitfield) &= ~VCID_MASK; \
|
|
(rxbitfield) |= (((vcid) << 16) & VCID_MASK); \
|
|
} while(0)
|
|
|
|
/** Mask to acess the rxBitField mbuf size */
|
|
#define CURRMBUFSIZE_MASK 0x0000ffff
|
|
|
|
/** return the rxBitField mbuf size */
|
|
#define IX_NPE_A_RXBITFIELD_CURRMBUFSIZE_GET( rxbitfield ) \
|
|
((rxbitfield) & CURRMBUFSIZE_MASK)
|
|
|
|
/** set the rxBitField mbuf size */
|
|
#define IX_NPE_A_RXBITFIELD_CURRMBUFSIZE_SET( rxbitfield, currmbufsize ) \
|
|
do { \
|
|
(rxbitfield) &= ~CURRMBUFSIZE_MASK; \
|
|
(rxbitfield) |= ((currmbufsize) & CURRMBUFSIZE_MASK); \
|
|
} while(0)
|
|
|
|
|
|
|
|
/**
|
|
* @brief Tx Descriptor definition
|
|
*/
|
|
typedef struct
|
|
{
|
|
UINT8 port; /**< Tx Port number */
|
|
UINT8 aalType; /**< AAL Type */
|
|
UINT16 currMbufLen; /**< mbuf length */
|
|
UINT32 atmCellHeader; /**< ATM cell header */
|
|
IX_OSAL_MBUF *pCurrMbuf; /**< pointer to mbuf */
|
|
unsigned char *pCurrMbufData; /**< Pointer to mbuf->dat */
|
|
IX_OSAL_MBUF *pNextMbuf; /**< Pointer to next mbuf */
|
|
UINT32 totalLen; /**< Total Length */
|
|
UINT32 aal5CrcResidue; /**< AAL5 CRC Residue */
|
|
} IxNpeA_TxAtmVc;
|
|
|
|
/* Changes to field sizes or orders must be reflected in the offset
|
|
* definitions above. */
|
|
|
|
|
|
|
|
|
|
/**
|
|
* @brief Rx Descriptor definition
|
|
*/
|
|
typedef struct
|
|
{
|
|
UINT32 rxBitField; /**< Received bit field */
|
|
UINT32 atmCellHeader; /**< ATM Cell Header */
|
|
UINT32 rsvdWord0; /**< Reserved field */
|
|
UINT16 currMbufLen; /**< Mbuf Length */
|
|
UINT8 timeLimit; /**< Payload Reassembly timeLimit (used for aal0_xx only) */
|
|
UINT8 rsvdByte0; /**< Reserved field */
|
|
UINT32 rsvdWord1; /**< Reserved field */
|
|
IX_OSAL_MBUF *pCurrMbuf; /**< Pointer to current mbuf */
|
|
unsigned char *pCurrMbufData; /**< Pointer to current mbuf->data */
|
|
IX_OSAL_MBUF *pNextMbuf; /**< Pointer to next mbuf */
|
|
UINT32 totalLen; /**< Total Length */
|
|
UINT32 aal5CrcResidue; /**< AAL5 CRC Residue */
|
|
} IxNpeA_RxAtmVc;
|
|
|
|
|
|
/**
|
|
* @brief NPE-A AAL Type
|
|
*/
|
|
typedef enum
|
|
{
|
|
IX_NPE_A_AAL_TYPE_INVALID = 0, /**< Invalid AAL type */
|
|
IX_NPE_A_AAL_TYPE_0_48 = 0x1, /**< AAL0 - 48 byte */
|
|
IX_NPE_A_AAL_TYPE_0_52 = 0x2, /**< AAL0 - 52 byte */
|
|
IX_NPE_A_AAL_TYPE_5 = 0x5, /**< AAL5 */
|
|
IX_NPE_A_AAL_TYPE_OAM = 0xF /**< OAM */
|
|
} IxNpeA_AalType;
|
|
|
|
/**
|
|
* @brief NPE-A Payload format 52-bytes & 48-bytes
|
|
*/
|
|
typedef enum
|
|
{
|
|
IX_NPE_A_52_BYTE_PAYLOAD = 0, /**< 52 byte payload */
|
|
IX_NPE_A_48_BYTE_PAYLOAD /**< 48 byte payload */
|
|
} IxNpeA_PayloadFormat;
|
|
|
|
/**
|
|
* @brief HSS Packetized NpePacket Descriptor Structure
|
|
*/
|
|
typedef struct
|
|
{
|
|
UINT8 status; /**< Status of the packet passed to the client */
|
|
UINT8 errorCount; /**< Number of errors */
|
|
UINT8 chainCount; /**< Mbuf chain count e.g. 0 - No mbuf chain */
|
|
UINT8 rsvdByte0; /**< Reserved byte to make the descriptor word align */
|
|
|
|
UINT16 packetLength; /**< Packet Length */
|
|
UINT16 rsvdShort0; /**< Reserved short to make the descriptor a word align */
|
|
|
|
IX_OSAL_MBUF *pRootMbuf; /**< Pointer to Root mbuf */
|
|
IX_OSAL_MBUF *pNextMbuf; /**< Pointer to next mbuf */
|
|
UINT8 *pMbufData; /**< Pointer to the current mbuf->data */
|
|
UINT32 mbufLength; /**< Current mbuf length */
|
|
|
|
} IxNpeA_NpePacketDescriptor;
|
|
|
|
|
|
#endif
|
|
/**
|
|
*@}
|
|
*/
|
|
|
|
#endif /* __doxygen_HIDE */
|