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![Vladimir Zapolskiy](/assets/img/avatar_default.png)
This change adds initial support for NXP LPC32x0 SoC series. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net> Acked-by: Marek Vasut <marek.vasut@gmail.com>
71 lines
2.0 KiB
C
71 lines
2.0 KiB
C
/*
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* Copyright (C) 2011 by Vladimir Zapolskiy <vz@mleia.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
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* MA 02110-1301, USA.
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*/
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#include <common.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/clk.h>
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#include <asm/arch/wdt.h>
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#include <asm/io.h>
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static struct clk_pm_regs *clk = (struct clk_pm_regs *)CLK_PM_BASE;
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static struct wdt_regs *wdt = (struct wdt_regs *)WDT_BASE;
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void reset_cpu(ulong addr)
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{
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/* Enable watchdog clock */
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setbits_le32(&clk->timclk_ctrl, CLK_TIMCLK_WATCHDOG);
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/* Reset pulse length is 13005 peripheral clock frames */
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writel(13000, &wdt->pulse);
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/* Force WDOG_RESET2 and RESOUT_N signal active */
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writel(WDTIM_MCTRL_RESFRC2 | WDTIM_MCTRL_RESFRC1 | WDTIM_MCTRL_M_RES2,
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&wdt->mctrl);
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while (1)
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/* NOP */;
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}
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#if defined(CONFIG_ARCH_CPU_INIT)
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int arch_cpu_init(void)
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{
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/*
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* It might be necessary to flush data cache, if U-boot is loaded
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* from kickstart bootloader, e.g. from S1L loader
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*/
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flush_dcache_all();
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return 0;
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}
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#else
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#error "You have to select CONFIG_ARCH_CPU_INIT"
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#endif
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#if defined(CONFIG_DISPLAY_CPUINFO)
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int print_cpuinfo(void)
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{
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printf("CPU: NXP LPC32XX\n");
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printf("CPU clock: %uMHz\n", get_hclk_pll_rate() / 1000000);
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printf("AHB bus clock: %uMHz\n", get_hclk_clk_rate() / 1000000);
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printf("Peripheral clock: %uMHz\n", get_periph_clk_rate() / 1000000);
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return 0;
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}
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#endif
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