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![Fabien Parent](/assets/img/avatar_default.png)
Add the implementation for the CLK_GATE_SETCLR_INV and CLK_GATE_NO_SETCLR flags. Signed-off-by: Fabien Parent <fparent@baylibre.com> Acked-by: Ryder Lee <ryder.lee@mediatek.com>
506 lines
12 KiB
C
506 lines
12 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* MediaTek common clock driver
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*
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* Copyright (C) 2018 MediaTek Inc.
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* Author: Ryder Lee <ryder.lee@mediatek.com>
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*/
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#include <common.h>
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#include <clk-uclass.h>
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#include <div64.h>
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#include <dm.h>
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#include <asm/io.h>
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#include "clk-mtk.h"
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#define REG_CON0 0
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#define REG_CON1 4
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#define CON0_BASE_EN BIT(0)
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#define CON0_PWR_ON BIT(0)
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#define CON0_ISO_EN BIT(1)
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#define CON1_PCW_CHG BIT(31)
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#define POSTDIV_MASK 0x7
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#define INTEGER_BITS 7
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/* scpsys clock off control */
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#define CLK_SCP_CFG0 0x200
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#define CLK_SCP_CFG1 0x204
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#define SCP_ARMCK_OFF_EN GENMASK(9, 0)
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#define SCP_AXICK_DCM_DIS_EN BIT(0)
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#define SCP_AXICK_26M_SEL_EN BIT(4)
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/* shared functions */
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/*
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* In case the rate change propagation to parent clocks is undesirable,
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* this function is recursively called to find the parent to calculate
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* the accurate frequency.
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*/
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static int mtk_clk_find_parent_rate(struct clk *clk, int id,
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const struct driver *drv)
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{
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struct clk parent = { .id = id, };
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if (drv) {
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struct udevice *dev;
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if (uclass_get_device_by_driver(UCLASS_CLK, drv, &dev))
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return -ENODEV;
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parent.dev = dev;
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} else {
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parent.dev = clk->dev;
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}
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return clk_get_rate(&parent);
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}
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static int mtk_clk_mux_set_parent(void __iomem *base, u32 parent,
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const struct mtk_composite *mux)
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{
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u32 val, index = 0;
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while (mux->parent[index] != parent)
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if (++index == mux->num_parents)
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return -EINVAL;
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/* switch mux to a select parent */
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val = readl(base + mux->mux_reg);
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val &= ~(mux->mux_mask << mux->mux_shift);
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val |= index << mux->mux_shift;
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writel(val, base + mux->mux_reg);
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return 0;
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}
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/* apmixedsys functions */
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static unsigned long __mtk_pll_recalc_rate(const struct mtk_pll_data *pll,
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u32 fin, u32 pcw, int postdiv)
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{
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int pcwbits = pll->pcwbits;
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int pcwfbits;
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u64 vco;
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u8 c = 0;
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/* The fractional part of the PLL divider. */
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pcwfbits = pcwbits > INTEGER_BITS ? pcwbits - INTEGER_BITS : 0;
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vco = (u64)fin * pcw;
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if (pcwfbits && (vco & GENMASK(pcwfbits - 1, 0)))
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c = 1;
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vco >>= pcwfbits;
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if (c)
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vco++;
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return ((unsigned long)vco + postdiv - 1) / postdiv;
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}
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/**
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* MediaTek PLLs are configured through their pcw value. The pcw value
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* describes a divider in the PLL feedback loop which consists of 7 bits
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* for the integer part and the remaining bits (if present) for the
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* fractional part. Also they have a 3 bit power-of-two post divider.
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*/
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static void mtk_pll_set_rate_regs(struct clk *clk, u32 pcw, int postdiv)
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{
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struct mtk_clk_priv *priv = dev_get_priv(clk->dev);
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const struct mtk_pll_data *pll = &priv->tree->plls[clk->id];
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u32 val;
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/* set postdiv */
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val = readl(priv->base + pll->pd_reg);
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val &= ~(POSTDIV_MASK << pll->pd_shift);
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val |= (ffs(postdiv) - 1) << pll->pd_shift;
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/* postdiv and pcw need to set at the same time if on same register */
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if (pll->pd_reg != pll->pcw_reg) {
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writel(val, priv->base + pll->pd_reg);
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val = readl(priv->base + pll->pcw_reg);
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}
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/* set pcw */
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val &= ~GENMASK(pll->pcw_shift + pll->pcwbits - 1, pll->pcw_shift);
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val |= pcw << pll->pcw_shift;
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val &= ~CON1_PCW_CHG;
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writel(val, priv->base + pll->pcw_reg);
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val |= CON1_PCW_CHG;
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writel(val, priv->base + pll->pcw_reg);
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udelay(20);
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}
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/**
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* mtk_pll_calc_values - calculate good values for a given input frequency.
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* @clk: The clk
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* @pcw: The pcw value (output)
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* @postdiv: The post divider (output)
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* @freq: The desired target frequency
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*/
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static void mtk_pll_calc_values(struct clk *clk, u32 *pcw, u32 *postdiv,
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u32 freq)
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{
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struct mtk_clk_priv *priv = dev_get_priv(clk->dev);
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const struct mtk_pll_data *pll = &priv->tree->plls[clk->id];
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unsigned long fmin = 1000 * MHZ;
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u64 _pcw;
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u32 val;
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if (freq > pll->fmax)
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freq = pll->fmax;
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for (val = 0; val < 5; val++) {
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*postdiv = 1 << val;
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if ((u64)freq * *postdiv >= fmin)
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break;
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}
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/* _pcw = freq * postdiv / xtal_rate * 2^pcwfbits */
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_pcw = ((u64)freq << val) << (pll->pcwbits - INTEGER_BITS);
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do_div(_pcw, priv->tree->xtal2_rate);
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*pcw = (u32)_pcw;
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}
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static ulong mtk_apmixedsys_set_rate(struct clk *clk, ulong rate)
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{
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u32 pcw = 0;
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u32 postdiv;
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mtk_pll_calc_values(clk, &pcw, &postdiv, rate);
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mtk_pll_set_rate_regs(clk, pcw, postdiv);
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return 0;
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}
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static ulong mtk_apmixedsys_get_rate(struct clk *clk)
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{
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struct mtk_clk_priv *priv = dev_get_priv(clk->dev);
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const struct mtk_pll_data *pll = &priv->tree->plls[clk->id];
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u32 postdiv;
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u32 pcw;
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postdiv = (readl(priv->base + pll->pd_reg) >> pll->pd_shift) &
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POSTDIV_MASK;
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postdiv = 1 << postdiv;
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pcw = readl(priv->base + pll->pcw_reg) >> pll->pcw_shift;
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pcw &= GENMASK(pll->pcwbits - 1, 0);
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return __mtk_pll_recalc_rate(pll, priv->tree->xtal2_rate,
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pcw, postdiv);
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}
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static int mtk_apmixedsys_enable(struct clk *clk)
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{
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struct mtk_clk_priv *priv = dev_get_priv(clk->dev);
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const struct mtk_pll_data *pll = &priv->tree->plls[clk->id];
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u32 r;
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r = readl(priv->base + pll->pwr_reg) | CON0_PWR_ON;
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writel(r, priv->base + pll->pwr_reg);
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udelay(1);
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r = readl(priv->base + pll->pwr_reg) & ~CON0_ISO_EN;
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writel(r, priv->base + pll->pwr_reg);
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udelay(1);
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r = readl(priv->base + pll->reg + REG_CON0);
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r |= pll->en_mask;
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writel(r, priv->base + pll->reg + REG_CON0);
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udelay(20);
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if (pll->flags & HAVE_RST_BAR) {
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r = readl(priv->base + pll->reg + REG_CON0);
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r |= pll->rst_bar_mask;
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writel(r, priv->base + pll->reg + REG_CON0);
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}
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return 0;
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}
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static int mtk_apmixedsys_disable(struct clk *clk)
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{
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struct mtk_clk_priv *priv = dev_get_priv(clk->dev);
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const struct mtk_pll_data *pll = &priv->tree->plls[clk->id];
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u32 r;
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if (pll->flags & HAVE_RST_BAR) {
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r = readl(priv->base + pll->reg + REG_CON0);
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r &= ~pll->rst_bar_mask;
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writel(r, priv->base + pll->reg + REG_CON0);
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}
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r = readl(priv->base + pll->reg + REG_CON0);
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r &= ~CON0_BASE_EN;
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writel(r, priv->base + pll->reg + REG_CON0);
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r = readl(priv->base + pll->pwr_reg) | CON0_ISO_EN;
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writel(r, priv->base + pll->pwr_reg);
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r = readl(priv->base + pll->pwr_reg) & ~CON0_PWR_ON;
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writel(r, priv->base + pll->pwr_reg);
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return 0;
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}
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/* topckgen functions */
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static ulong mtk_factor_recalc_rate(const struct mtk_fixed_factor *fdiv,
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ulong parent_rate)
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{
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u64 rate = parent_rate * fdiv->mult;
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do_div(rate, fdiv->div);
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return rate;
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}
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static int mtk_topckgen_get_factor_rate(struct clk *clk, u32 off)
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{
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struct mtk_clk_priv *priv = dev_get_priv(clk->dev);
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const struct mtk_fixed_factor *fdiv = &priv->tree->fdivs[off];
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ulong rate;
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switch (fdiv->flags & CLK_PARENT_MASK) {
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case CLK_PARENT_APMIXED:
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rate = mtk_clk_find_parent_rate(clk, fdiv->parent,
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DM_GET_DRIVER(mtk_clk_apmixedsys));
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break;
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case CLK_PARENT_TOPCKGEN:
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rate = mtk_clk_find_parent_rate(clk, fdiv->parent, NULL);
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break;
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default:
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rate = priv->tree->xtal_rate;
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}
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return mtk_factor_recalc_rate(fdiv, rate);
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}
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static int mtk_topckgen_get_mux_rate(struct clk *clk, u32 off)
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{
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struct mtk_clk_priv *priv = dev_get_priv(clk->dev);
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const struct mtk_composite *mux = &priv->tree->muxes[off];
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u32 index;
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index = readl(priv->base + mux->mux_reg);
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index &= mux->mux_mask << mux->mux_shift;
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index = index >> mux->mux_shift;
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if (mux->parent[index])
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return mtk_clk_find_parent_rate(clk, mux->parent[index],
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NULL);
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return priv->tree->xtal_rate;
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}
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static ulong mtk_topckgen_get_rate(struct clk *clk)
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{
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struct mtk_clk_priv *priv = dev_get_priv(clk->dev);
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if (clk->id < priv->tree->fdivs_offs)
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return priv->tree->fclks[clk->id].rate;
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else if (clk->id < priv->tree->muxes_offs)
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return mtk_topckgen_get_factor_rate(clk, clk->id -
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priv->tree->fdivs_offs);
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else
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return mtk_topckgen_get_mux_rate(clk, clk->id -
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priv->tree->muxes_offs);
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}
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static int mtk_topckgen_enable(struct clk *clk)
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{
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struct mtk_clk_priv *priv = dev_get_priv(clk->dev);
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const struct mtk_composite *mux;
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u32 val;
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if (clk->id < priv->tree->muxes_offs)
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return 0;
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mux = &priv->tree->muxes[clk->id - priv->tree->muxes_offs];
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if (mux->gate_shift < 0)
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return 0;
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/* enable clock gate */
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val = readl(priv->base + mux->gate_reg);
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val &= ~BIT(mux->gate_shift);
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writel(val, priv->base + mux->gate_reg);
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if (mux->flags & CLK_DOMAIN_SCPSYS) {
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/* enable scpsys clock off control */
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writel(SCP_ARMCK_OFF_EN, priv->base + CLK_SCP_CFG0);
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writel(SCP_AXICK_DCM_DIS_EN | SCP_AXICK_26M_SEL_EN,
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priv->base + CLK_SCP_CFG1);
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}
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return 0;
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}
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static int mtk_topckgen_disable(struct clk *clk)
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{
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struct mtk_clk_priv *priv = dev_get_priv(clk->dev);
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const struct mtk_composite *mux;
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u32 val;
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if (clk->id < priv->tree->muxes_offs)
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return 0;
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mux = &priv->tree->muxes[clk->id - priv->tree->muxes_offs];
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if (mux->gate_shift < 0)
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return 0;
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/* disable clock gate */
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val = readl(priv->base + mux->gate_reg);
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val |= BIT(mux->gate_shift);
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writel(val, priv->base + mux->gate_reg);
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return 0;
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}
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static int mtk_topckgen_set_parent(struct clk *clk, struct clk *parent)
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{
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struct mtk_clk_priv *priv = dev_get_priv(clk->dev);
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if (clk->id < priv->tree->muxes_offs)
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return 0;
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return mtk_clk_mux_set_parent(priv->base, parent->id,
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&priv->tree->muxes[clk->id - priv->tree->muxes_offs]);
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}
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/* CG functions */
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static int mtk_clk_gate_enable(struct clk *clk)
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{
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struct mtk_cg_priv *priv = dev_get_priv(clk->dev);
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const struct mtk_gate *gate = &priv->gates[clk->id];
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u32 bit = BIT(gate->shift);
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switch (gate->flags & CLK_GATE_MASK) {
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case CLK_GATE_SETCLR:
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writel(bit, priv->base + gate->regs->clr_ofs);
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break;
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case CLK_GATE_SETCLR_INV:
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writel(bit, priv->base + gate->regs->set_ofs);
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break;
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case CLK_GATE_NO_SETCLR:
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clrsetbits_le32(priv->base + gate->regs->sta_ofs, bit, 0);
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break;
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case CLK_GATE_NO_SETCLR_INV:
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clrsetbits_le32(priv->base + gate->regs->sta_ofs, bit, bit);
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break;
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default:
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return -EINVAL;
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}
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return 0;
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}
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static int mtk_clk_gate_disable(struct clk *clk)
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{
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struct mtk_cg_priv *priv = dev_get_priv(clk->dev);
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const struct mtk_gate *gate = &priv->gates[clk->id];
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u32 bit = BIT(gate->shift);
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switch (gate->flags & CLK_GATE_MASK) {
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case CLK_GATE_SETCLR:
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writel(bit, priv->base + gate->regs->set_ofs);
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break;
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case CLK_GATE_SETCLR_INV:
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writel(bit, priv->base + gate->regs->clr_ofs);
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break;
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case CLK_GATE_NO_SETCLR:
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clrsetbits_le32(priv->base + gate->regs->sta_ofs, bit, bit);
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break;
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case CLK_GATE_NO_SETCLR_INV:
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clrsetbits_le32(priv->base + gate->regs->sta_ofs, bit, 0);
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break;
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default:
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return -EINVAL;
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}
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return 0;
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}
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static ulong mtk_clk_gate_get_rate(struct clk *clk)
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{
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struct mtk_cg_priv *priv = dev_get_priv(clk->dev);
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const struct mtk_gate *gate = &priv->gates[clk->id];
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switch (gate->flags & CLK_PARENT_MASK) {
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case CLK_PARENT_APMIXED:
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return mtk_clk_find_parent_rate(clk, gate->parent,
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DM_GET_DRIVER(mtk_clk_apmixedsys));
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break;
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case CLK_PARENT_TOPCKGEN:
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return mtk_clk_find_parent_rate(clk, gate->parent,
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DM_GET_DRIVER(mtk_clk_topckgen));
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break;
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default:
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return priv->tree->xtal_rate;
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}
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}
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const struct clk_ops mtk_clk_apmixedsys_ops = {
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.enable = mtk_apmixedsys_enable,
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.disable = mtk_apmixedsys_disable,
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.set_rate = mtk_apmixedsys_set_rate,
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.get_rate = mtk_apmixedsys_get_rate,
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};
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const struct clk_ops mtk_clk_topckgen_ops = {
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.enable = mtk_topckgen_enable,
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.disable = mtk_topckgen_disable,
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.get_rate = mtk_topckgen_get_rate,
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.set_parent = mtk_topckgen_set_parent,
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};
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const struct clk_ops mtk_clk_gate_ops = {
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.enable = mtk_clk_gate_enable,
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.disable = mtk_clk_gate_disable,
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.get_rate = mtk_clk_gate_get_rate,
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};
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int mtk_common_clk_init(struct udevice *dev,
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const struct mtk_clk_tree *tree)
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{
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struct mtk_clk_priv *priv = dev_get_priv(dev);
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priv->base = dev_read_addr_ptr(dev);
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if (!priv->base)
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return -ENOENT;
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priv->tree = tree;
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return 0;
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}
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int mtk_common_clk_gate_init(struct udevice *dev,
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const struct mtk_clk_tree *tree,
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const struct mtk_gate *gates)
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{
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struct mtk_cg_priv *priv = dev_get_priv(dev);
|
|
|
|
priv->base = dev_read_addr_ptr(dev);
|
|
if (!priv->base)
|
|
return -ENOENT;
|
|
|
|
priv->tree = tree;
|
|
priv->gates = gates;
|
|
|
|
return 0;
|
|
}
|