Michal Simek 39523bef29 zynq: slcr: Wait 100ms till clk is properly setup ... If you don't wait you will loose the first sent packet even all bits in emacps are correctly setup. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>		2013-08-12 08:59:55 +02:00
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cpu	zynq: slcr: Wait 100ms till clk is properly setup	2013-08-12 08:59:55 +02:00
dts	Merge branch 'master' of git://git.denx.de/u-boot-arm	2013-07-12 10:36:48 -04:00
imx-common	Add GPL-2.0+ SPDX-License-Identifier to source files	2013-07-24 09:44:38 -04:00
include/asm	zynq: Add new ddrc driver for ECC support	2013-08-12 08:59:55 +02:00
lib	Merge branch 'master' of git://git.denx.de/u-boot-i2c	2013-07-24 09:50:24 -04:00
config.mk	Add GPL-2.0+ SPDX-License-Identifier to source files	2013-07-24 09:44:38 -04:00