mirror of
https://github.com/brain-hackers/u-boot-brain
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83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
332 lines
8.9 KiB
C
332 lines
8.9 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright 2008 Freescale Semiconductor, Inc.
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*/
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#include <common.h>
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#include <fsl_ddr_sdram.h>
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#include <fsl_ddr.h>
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/*
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* Calculate the Density of each Physical Rank.
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* Returned size is in bytes.
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*
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* Study these table from Byte 31 of JEDEC SPD Spec.
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*
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* DDR I DDR II
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* Bit Size Size
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* --- ----- ------
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* 7 high 512MB 512MB
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* 6 256MB 256MB
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* 5 128MB 128MB
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* 4 64MB 16GB
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* 3 32MB 8GB
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* 2 16MB 4GB
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* 1 2GB 2GB
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* 0 low 1GB 1GB
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*
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* Reorder Table to be linear by stripping the bottom
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* 2 or 5 bits off and shifting them up to the top.
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*/
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static unsigned long long
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compute_ranksize(unsigned int mem_type, unsigned char row_dens)
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{
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unsigned long long bsize;
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/* Bottom 2 bits up to the top. */
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bsize = ((row_dens >> 2) | ((row_dens & 3) << 6));
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bsize <<= 24ULL;
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debug("DDR: DDR I rank density = 0x%16llx\n", bsize);
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return bsize;
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}
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/*
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* Convert a two-nibble BCD value into a cycle time.
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* While the spec calls for nano-seconds, picos are returned.
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*
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* This implements the tables for bytes 9, 23 and 25 for both
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* DDR I and II. No allowance for distinguishing the invalid
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* fields absent for DDR I yet present in DDR II is made.
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* (That is, cycle times of .25, .33, .66 and .75 ns are
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* allowed for both DDR II and I.)
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*/
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static unsigned int
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convert_bcd_tenths_to_cycle_time_ps(unsigned int spd_val)
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{
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/* Table look up the lower nibble, allow DDR I & II. */
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unsigned int tenths_ps[16] = {
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0,
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100,
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200,
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300,
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400,
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500,
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600,
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700,
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800,
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900,
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250, /* This and the next 3 entries valid ... */
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330, /* ... only for tCK calculations. */
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660,
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750,
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0, /* undefined */
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0 /* undefined */
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};
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unsigned int whole_ns = (spd_val & 0xF0) >> 4;
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unsigned int tenth_ns = spd_val & 0x0F;
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unsigned int ps = whole_ns * 1000 + tenths_ps[tenth_ns];
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return ps;
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}
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static unsigned int
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convert_bcd_hundredths_to_cycle_time_ps(unsigned int spd_val)
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{
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unsigned int tenth_ns = (spd_val & 0xF0) >> 4;
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unsigned int hundredth_ns = spd_val & 0x0F;
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unsigned int ps = tenth_ns * 100 + hundredth_ns * 10;
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return ps;
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}
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static unsigned int byte40_table_ps[8] = {
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0,
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250,
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330,
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500,
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660,
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750,
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0, /* supposed to be RFC, but not sure what that means */
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0 /* Undefined */
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};
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static unsigned int
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compute_trfc_ps_from_spd(unsigned char trctrfc_ext, unsigned char trfc)
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{
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return ((trctrfc_ext & 0x1) * 256 + trfc) * 1000
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+ byte40_table_ps[(trctrfc_ext >> 1) & 0x7];
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}
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static unsigned int
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compute_trc_ps_from_spd(unsigned char trctrfc_ext, unsigned char trc)
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{
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return trc * 1000 + byte40_table_ps[(trctrfc_ext >> 4) & 0x7];
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}
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/*
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* tCKmax from DDR I SPD Byte 43
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*
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* Bits 7:2 == whole ns
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* Bits 1:0 == quarter ns
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* 00 == 0.00 ns
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* 01 == 0.25 ns
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* 10 == 0.50 ns
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* 11 == 0.75 ns
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*
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* Returns picoseconds.
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*/
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static unsigned int
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compute_tckmax_from_spd_ps(unsigned int byte43)
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{
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return (byte43 >> 2) * 1000 + (byte43 & 0x3) * 250;
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}
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/*
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* Determine Refresh Rate. Ignore self refresh bit on DDR I.
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* Table from SPD Spec, Byte 12, converted to picoseconds and
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* filled in with "default" normal values.
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*/
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static unsigned int
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determine_refresh_rate_ps(const unsigned int spd_refresh)
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{
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unsigned int refresh_time_ps[8] = {
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15625000, /* 0 Normal 1.00x */
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3900000, /* 1 Reduced .25x */
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7800000, /* 2 Extended .50x */
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31300000, /* 3 Extended 2.00x */
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62500000, /* 4 Extended 4.00x */
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125000000, /* 5 Extended 8.00x */
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15625000, /* 6 Normal 1.00x filler */
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15625000, /* 7 Normal 1.00x filler */
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};
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return refresh_time_ps[spd_refresh & 0x7];
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}
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/*
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* The purpose of this function is to compute a suitable
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* CAS latency given the DRAM clock period. The SPD only
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* defines at most 3 CAS latencies. Typically the slower in
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* frequency the DIMM runs at, the shorter its CAS latency can be.
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* If the DIMM is operating at a sufficiently low frequency,
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* it may be able to run at a CAS latency shorter than the
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* shortest SPD-defined CAS latency.
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*
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* If a CAS latency is not found, 0 is returned.
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*
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* Do this by finding in the standard speed bin table the longest
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* tCKmin that doesn't exceed the value of mclk_ps (tCK).
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*
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* An assumption made is that the SDRAM device allows the
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* CL to be programmed for a value that is lower than those
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* advertised by the SPD. This is not always the case,
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* as those modes not defined in the SPD are optional.
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*
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* CAS latency de-rating based upon values JEDEC Standard No. 79-E
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* Table 11.
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*
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* ordinal 2, ddr1_speed_bins[1] contains tCK for CL=2
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*/
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/* CL2.0 CL2.5 CL3.0 */
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unsigned short ddr1_speed_bins[] = {0, 7500, 6000, 5000 };
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unsigned int
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compute_derated_DDR1_CAS_latency(unsigned int mclk_ps)
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{
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const unsigned int num_speed_bins = ARRAY_SIZE(ddr1_speed_bins);
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unsigned int lowest_tCKmin_found = 0;
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unsigned int lowest_tCKmin_CL = 0;
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unsigned int i;
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debug("mclk_ps = %u\n", mclk_ps);
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for (i = 0; i < num_speed_bins; i++) {
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unsigned int x = ddr1_speed_bins[i];
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debug("i=%u, x = %u, lowest_tCKmin_found = %u\n",
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i, x, lowest_tCKmin_found);
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if (x && lowest_tCKmin_found <= x && x <= mclk_ps) {
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lowest_tCKmin_found = x;
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lowest_tCKmin_CL = i + 1;
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}
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}
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debug("lowest_tCKmin_CL = %u\n", lowest_tCKmin_CL);
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return lowest_tCKmin_CL;
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}
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/*
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* ddr_compute_dimm_parameters for DDR1 SPD
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*
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* Compute DIMM parameters based upon the SPD information in spd.
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* Writes the results to the dimm_params_t structure pointed by pdimm.
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*
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* FIXME: use #define for the retvals
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*/
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unsigned int ddr_compute_dimm_parameters(const unsigned int ctrl_num,
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const ddr1_spd_eeprom_t *spd,
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dimm_params_t *pdimm,
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unsigned int dimm_number)
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{
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unsigned int retval;
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if (spd->mem_type) {
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if (spd->mem_type != SPD_MEMTYPE_DDR) {
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printf("DIMM %u: is not a DDR1 SPD.\n", dimm_number);
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return 1;
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}
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} else {
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memset(pdimm, 0, sizeof(dimm_params_t));
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return 1;
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}
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retval = ddr1_spd_check(spd);
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if (retval) {
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printf("DIMM %u: failed checksum\n", dimm_number);
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return 2;
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}
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/*
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* The part name in ASCII in the SPD EEPROM is not null terminated.
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* Guarantee null termination here by presetting all bytes to 0
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* and copying the part name in ASCII from the SPD onto it
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*/
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memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
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memcpy(pdimm->mpart, spd->mpart, sizeof(pdimm->mpart) - 1);
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/* DIMM organization parameters */
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pdimm->n_ranks = spd->nrows;
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pdimm->rank_density = compute_ranksize(spd->mem_type, spd->bank_dens);
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pdimm->capacity = pdimm->n_ranks * pdimm->rank_density;
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pdimm->data_width = spd->dataw_lsb;
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pdimm->primary_sdram_width = spd->primw;
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pdimm->ec_sdram_width = spd->ecw;
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/*
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* FIXME: Need to determine registered_dimm status.
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* 1 == register buffered
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* 0 == unbuffered
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*/
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pdimm->registered_dimm = 0; /* unbuffered */
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/* SDRAM device parameters */
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pdimm->n_row_addr = spd->nrow_addr;
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pdimm->n_col_addr = spd->ncol_addr;
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pdimm->n_banks_per_sdram_device = spd->nbanks;
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pdimm->edc_config = spd->config;
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pdimm->burst_lengths_bitmask = spd->burstl;
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/*
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* Calculate the Maximum Data Rate based on the Minimum Cycle time.
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* The SPD clk_cycle field (tCKmin) is measured in tenths of
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* nanoseconds and represented as BCD.
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*/
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pdimm->tckmin_x_ps
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= convert_bcd_tenths_to_cycle_time_ps(spd->clk_cycle);
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pdimm->tckmin_x_minus_1_ps
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= convert_bcd_tenths_to_cycle_time_ps(spd->clk_cycle2);
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pdimm->tckmin_x_minus_2_ps
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= convert_bcd_tenths_to_cycle_time_ps(spd->clk_cycle3);
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pdimm->tckmax_ps = compute_tckmax_from_spd_ps(spd->tckmax);
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/*
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* Compute CAS latencies defined by SPD
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* The SPD caslat_x should have at least 1 and at most 3 bits set.
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*
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* If cas_lat after masking is 0, the __ilog2 function returns
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* 255 into the variable. This behavior is abused once.
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*/
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pdimm->caslat_x = __ilog2(spd->cas_lat);
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pdimm->caslat_x_minus_1 = __ilog2(spd->cas_lat
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& ~(1 << pdimm->caslat_x));
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pdimm->caslat_x_minus_2 = __ilog2(spd->cas_lat
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& ~(1 << pdimm->caslat_x)
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& ~(1 << pdimm->caslat_x_minus_1));
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/* Compute CAS latencies below that defined by SPD */
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pdimm->caslat_lowest_derated = compute_derated_DDR1_CAS_latency(
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get_memory_clk_period_ps(ctrl_num));
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/* Compute timing parameters */
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pdimm->trcd_ps = spd->trcd * 250;
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pdimm->trp_ps = spd->trp * 250;
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pdimm->tras_ps = spd->tras * 1000;
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pdimm->twr_ps = mclk_to_picos(ctrl_num, 3);
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pdimm->twtr_ps = mclk_to_picos(ctrl_num, 1);
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pdimm->trfc_ps = compute_trfc_ps_from_spd(0, spd->trfc);
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pdimm->trrd_ps = spd->trrd * 250;
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pdimm->trc_ps = compute_trc_ps_from_spd(0, spd->trc);
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pdimm->refresh_rate_ps = determine_refresh_rate_ps(spd->refresh);
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pdimm->tis_ps = convert_bcd_hundredths_to_cycle_time_ps(spd->ca_setup);
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pdimm->tih_ps = convert_bcd_hundredths_to_cycle_time_ps(spd->ca_hold);
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pdimm->tds_ps
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= convert_bcd_hundredths_to_cycle_time_ps(spd->data_setup);
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pdimm->tdh_ps
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= convert_bcd_hundredths_to_cycle_time_ps(spd->data_hold);
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pdimm->trtp_ps = mclk_to_picos(ctrl_num, 2); /* By the book. */
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pdimm->tdqsq_max_ps = spd->tdqsq * 10;
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pdimm->tqhs_ps = spd->tqhs * 10;
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return 0;
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}
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