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https://github.com/brain-hackers/u-boot-brain
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39245c8699
Based on the definitive guide to EMIF configuration[1] certain registers that we have been modifying (and are documented registers) should be left in their reset values rather than modified. This has been tested on AM335x GP EVM and Beaglebone White. [1]: http://processors.wiki.ti.com/index.php/AM335x_EMIF_Configuration_tips Cc: Enric Balletbo i Serra <eballetbo@iseebcn.com> Cc: Javier Martinez Canillas <javier@dowhile0.org> Cc: Heiko Schocher <hs@denx.de> Cc: Lars Poeschel <poeschel@lemonage.de> Signed-off-by: Tom Rini <trini@ti.com> Tested-by: Matt Porter <matt.porter@linaro.org>
239 lines
6.4 KiB
C
239 lines
6.4 KiB
C
/*
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* Board functions for TI AM335X based dxr2 board
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* (C) Copyright 2013 Siemens Schweiz AG
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* (C) Heiko Schocher, DENX Software Engineering, hs@denx.de.
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*
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* Based on:
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*
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* Board functions for TI AM335X based boards
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* u-boot:/board/ti/am335x/board.c
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*
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* Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <errno.h>
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#include <spl.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/omap.h>
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#include <asm/arch/ddr_defs.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/gpio.h>
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#include <asm/arch/mmc_host_def.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/io.h>
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#include <asm/emif.h>
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#include <asm/gpio.h>
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#include <i2c.h>
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#include <miiphy.h>
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#include <cpsw.h>
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#include <watchdog.h>
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#include "board.h"
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#include "../common/factoryset.h"
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DECLARE_GLOBAL_DATA_PTR;
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#ifdef CONFIG_SPL_BUILD
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static struct dxr2_baseboard_id __attribute__((section(".data"))) settings;
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/* @303MHz-i0 */
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const struct ddr3_data ddr3_default = {
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0x33524444, 0x56312e34, 0x0080, 0x0000, 0x0038, 0x003E, 0x00A4,
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0x0075, 0x0888A39B, 0x26247FDA, 0x501F821F, 0x00100206, 0x61A44A32,
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0x00000618, 0x0000014A,
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};
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static void set_default_ddr3_timings(void)
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{
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printf("Set default DDR3 settings\n");
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settings.ddr3 = ddr3_default;
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}
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static void print_ddr3_timings(void)
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{
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printf("\n\nDDR3 Timing parameters:\n");
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printf("Diff Eeprom Default\n");
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PRINTARGS(magic);
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PRINTARGS(version);
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PRINTARGS(ddr3_sratio);
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PRINTARGS(iclkout);
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PRINTARGS(dt0rdsratio0);
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PRINTARGS(dt0wdsratio0);
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PRINTARGS(dt0fwsratio0);
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PRINTARGS(dt0wrsratio0);
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PRINTARGS(sdram_tim1);
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PRINTARGS(sdram_tim2);
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PRINTARGS(sdram_tim3);
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PRINTARGS(emif_ddr_phy_ctlr_1);
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PRINTARGS(sdram_config);
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PRINTARGS(ref_ctrl);
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PRINTARGS(ioctr_val);
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}
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static void print_chip_data(void)
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{
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printf("\n");
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printf("Device: '%s'\n", settings.chip.sdevname);
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printf("HW version: '%s'\n", settings.chip.shwver);
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}
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#endif /* CONFIG_SPL_BUILD */
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/*
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* Read header information from EEPROM into global structure.
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*/
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static int read_eeprom(void)
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{
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/* Check if baseboard eeprom is available */
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if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) {
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printf("Could not probe the EEPROM; something fundamentally wrong on the I2C bus.\n");
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return 1;
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}
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#ifdef CONFIG_SPL_BUILD
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/* Read Siemens eeprom data (DDR3) */
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if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, EEPROM_ADDR_DDR3, 2,
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(uchar *)&settings.ddr3, sizeof(struct ddr3_data))) {
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printf("Could not read the EEPROM; something fundamentally wrong on the I2C bus.\nUse default DDR3 timings\n");
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set_default_ddr3_timings();
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}
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/* Read Siemens eeprom data (CHIP) */
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if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, EEPROM_ADDR_CHIP, 2,
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(uchar *)&settings.chip, sizeof(settings.chip)))
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printf("Could not read chip settings\n");
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if (ddr3_default.magic == settings.ddr3.magic &&
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ddr3_default.version == settings.ddr3.version) {
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printf("Using DDR3 settings from EEPROM\n");
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} else {
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if (ddr3_default.magic != settings.ddr3.magic)
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printf("Error: No valid DDR3 data in eeprom.\n");
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if (ddr3_default.version != settings.ddr3.version)
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printf("Error: DDR3 data version does not match.\n");
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printf("Using default settings\n");
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set_default_ddr3_timings();
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}
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if (MAGIC_CHIP == settings.chip.magic) {
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printf("Valid chip data in eeprom\n");
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print_chip_data();
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} else {
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printf("Error: No chip data in eeprom\n");
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}
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print_ddr3_timings();
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#endif
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return 0;
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}
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#ifdef CONFIG_SPL_BUILD
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static void board_init_ddr(void)
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{
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struct emif_regs dxr2_ddr3_emif_reg_data = {
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.zq_config = 0x50074BE4,
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};
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struct ddr_data dxr2_ddr3_data = {
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};
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struct cmd_control dxr2_ddr3_cmd_ctrl_data = {
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};
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/* pass values from eeprom */
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dxr2_ddr3_emif_reg_data.sdram_tim1 = settings.ddr3.sdram_tim1;
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dxr2_ddr3_emif_reg_data.sdram_tim2 = settings.ddr3.sdram_tim2;
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dxr2_ddr3_emif_reg_data.sdram_tim3 = settings.ddr3.sdram_tim3;
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dxr2_ddr3_emif_reg_data.emif_ddr_phy_ctlr_1 =
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settings.ddr3.emif_ddr_phy_ctlr_1;
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dxr2_ddr3_emif_reg_data.sdram_config = settings.ddr3.sdram_config;
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dxr2_ddr3_emif_reg_data.ref_ctrl = settings.ddr3.ref_ctrl;
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dxr2_ddr3_data.datardsratio0 = settings.ddr3.dt0rdsratio0;
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dxr2_ddr3_data.datawdsratio0 = settings.ddr3.dt0wdsratio0;
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dxr2_ddr3_data.datafwsratio0 = settings.ddr3.dt0fwsratio0;
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dxr2_ddr3_data.datawrsratio0 = settings.ddr3.dt0wrsratio0;
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dxr2_ddr3_cmd_ctrl_data.cmd0csratio = settings.ddr3.ddr3_sratio;
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dxr2_ddr3_cmd_ctrl_data.cmd0iclkout = settings.ddr3.iclkout;
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dxr2_ddr3_cmd_ctrl_data.cmd1csratio = settings.ddr3.ddr3_sratio;
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dxr2_ddr3_cmd_ctrl_data.cmd1iclkout = settings.ddr3.iclkout;
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dxr2_ddr3_cmd_ctrl_data.cmd2csratio = settings.ddr3.ddr3_sratio;
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dxr2_ddr3_cmd_ctrl_data.cmd2iclkout = settings.ddr3.iclkout;
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config_ddr(DDR_PLL_FREQ, settings.ddr3.ioctr_val, &dxr2_ddr3_data,
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&dxr2_ddr3_cmd_ctrl_data, &dxr2_ddr3_emif_reg_data, 0);
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}
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static void spl_siemens_board_init(void)
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{
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return;
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}
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#endif /* if def CONFIG_SPL_BUILD */
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#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
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(defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
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static void cpsw_control(int enabled)
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{
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/* VTP can be added here */
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return;
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}
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static struct cpsw_slave_data cpsw_slaves[] = {
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{
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.slave_reg_ofs = 0x208,
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.sliver_reg_ofs = 0xd80,
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.phy_id = 0,
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.phy_if = PHY_INTERFACE_MODE_MII,
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},
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};
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static struct cpsw_platform_data cpsw_data = {
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.mdio_base = CPSW_MDIO_BASE,
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.cpsw_base = CPSW_BASE,
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.mdio_div = 0xff,
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.channels = 4,
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.cpdma_reg_ofs = 0x800,
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.slaves = 1,
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.slave_data = cpsw_slaves,
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.ale_reg_ofs = 0xd00,
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.ale_entries = 1024,
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.host_port_reg_ofs = 0x108,
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.hw_stats_reg_ofs = 0x900,
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.bd_ram_ofs = 0x2000,
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.mac_control = (1 << 5),
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.control = cpsw_control,
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.host_port_num = 0,
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.version = CPSW_CTRL_VERSION_2,
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};
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#if defined(CONFIG_DRIVER_TI_CPSW) || \
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(defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET))
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int board_eth_init(bd_t *bis)
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{
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struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
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int n = 0;
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int rv;
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factoryset_setenv();
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/* Set rgmii mode and enable rmii clock to be sourced from chip */
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writel((RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE), &cdev->miisel);
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rv = cpsw_register(&cpsw_data);
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if (rv < 0)
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printf("Error %d registering CPSW switch\n", rv);
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else
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n += rv;
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return n;
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}
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#endif /* #if defined(CONFIG_DRIVER_TI_CPSW) */
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#endif /* #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) */
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#include "../common/board.c"
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