mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-29 05:18:51 +09:00
![Simon Glass](/assets/img/avatar_default.png)
Update board_init() to increase the ARM clock to the maximum speed on veyron boards. This makes quite a large difference in performance. With this change, speed goes from about 750 DMIPS to 2720 DMIPs. Signed-off-by: Simon Glass <sjg@chromium.org>
290 lines
5.6 KiB
C
290 lines
5.6 KiB
C
/*
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* (C) Copyright 2015 Google, Inc
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <clk.h>
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#include <dm.h>
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#include <ram.h>
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#include <syscon.h>
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/periph.h>
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#include <asm/arch/pmu_rk3288.h>
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#include <asm/arch/boot_mode.h>
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#include <asm/gpio.h>
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#include <dm/pinctrl.h>
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#include <dt-bindings/clock/rk3288-cru.h>
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#include <power/regulator.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define PMU_BASE 0xff730000
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static void setup_boot_mode(void)
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{
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struct rk3288_pmu *const pmu = (void *)PMU_BASE;
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int boot_mode = readl(&pmu->sys_reg[0]);
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debug("boot mode %x.\n", boot_mode);
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/* Clear boot mode */
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writel(BOOT_NORMAL, &pmu->sys_reg[0]);
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switch (boot_mode) {
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case BOOT_FASTBOOT:
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printf("enter fastboot!\n");
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setenv("preboot", "setenv preboot; fastboot usb0");
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break;
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case BOOT_UMS:
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printf("enter UMS!\n");
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setenv("preboot", "setenv preboot; if mmc dev 0;"
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"then ums mmc 0; else ums mmc 1;fi");
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break;
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}
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}
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__weak int rk_board_late_init(void)
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{
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return 0;
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}
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int board_late_init(void)
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{
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setup_boot_mode();
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return rk_board_late_init();
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}
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#ifndef CONFIG_ROCKCHIP_SPL_BACK_TO_BROM
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static int veyron_init(void)
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{
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struct udevice *dev;
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struct clk clk;
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int ret;
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ret = regulator_get_by_platname("vdd_arm", &dev);
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if (ret)
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return ret;
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/* Slowly raise to max CPU voltage to prevent overshoot */
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ret = regulator_set_value(dev, 1200000);
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if (ret)
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return ret;
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udelay(175); /* Must wait for voltage to stabilize, 2mV/us */
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ret = regulator_set_value(dev, 1400000);
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if (ret)
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return ret;
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udelay(100); /* Must wait for voltage to stabilize, 2mV/us */
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ret = rockchip_get_clk(&clk.dev);
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if (ret)
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return ret;
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clk.id = PLL_APLL;
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ret = clk_set_rate(&clk, 1800000000);
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if (IS_ERR_VALUE(ret))
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return ret;
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return 0;
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}
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#endif
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int board_init(void)
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{
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#ifdef CONFIG_ROCKCHIP_SPL_BACK_TO_BROM
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struct udevice *pinctrl;
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int ret;
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/*
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* We need to implement sdcard iomux here for the further
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* initlization, otherwise, it'll hit sdcard command sending
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* timeout exception.
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*/
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ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl);
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if (ret) {
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debug("%s: Cannot find pinctrl device\n", __func__);
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goto err;
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}
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ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_SDCARD);
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if (ret) {
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debug("%s: Failed to set up SD card\n", __func__);
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goto err;
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}
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return 0;
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err:
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printf("board_init: Error %d\n", ret);
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/* No way to report error here */
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hang();
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return -1;
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#else
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int ret;
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/* We do some SoC one time setting here */
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if (!fdt_node_check_compatible(gd->fdt_blob, 0, "google,veyron")) {
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ret = veyron_init();
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if (ret)
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return ret;
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}
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return 0;
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#endif
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}
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int dram_init(void)
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{
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struct ram_info ram;
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struct udevice *dev;
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int ret;
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ret = uclass_get_device(UCLASS_RAM, 0, &dev);
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if (ret) {
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debug("DRAM init failed: %d\n", ret);
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return ret;
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}
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ret = ram_get_info(dev, &ram);
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if (ret) {
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debug("Cannot get DRAM size: %d\n", ret);
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return ret;
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}
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debug("SDRAM base=%lx, size=%x\n", ram.base, ram.size);
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gd->ram_size = ram.size;
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return 0;
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}
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#ifndef CONFIG_SYS_DCACHE_OFF
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void enable_caches(void)
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{
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/* Enable D-cache. I-cache is already enabled in start.S */
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dcache_enable();
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}
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#endif
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#if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG)
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#include <usb.h>
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#include <usb/dwc2_udc.h>
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static struct dwc2_plat_otg_data rk3288_otg_data = {
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.rx_fifo_sz = 512,
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.np_tx_fifo_sz = 16,
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.tx_fifo_sz = 128,
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};
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int board_usb_init(int index, enum usb_init_type init)
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{
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int node, phy_node;
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const char *mode;
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bool matched = false;
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const void *blob = gd->fdt_blob;
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u32 grf_phy_offset;
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/* find the usb_otg node */
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node = fdt_node_offset_by_compatible(blob, -1,
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"rockchip,rk3288-usb");
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while (node > 0) {
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mode = fdt_getprop(blob, node, "dr_mode", NULL);
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if (mode && strcmp(mode, "otg") == 0) {
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matched = true;
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break;
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}
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node = fdt_node_offset_by_compatible(blob, node,
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"rockchip,rk3288-usb");
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}
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if (!matched) {
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debug("Not found usb_otg device\n");
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return -ENODEV;
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}
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rk3288_otg_data.regs_otg = fdtdec_get_addr(blob, node, "reg");
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node = fdtdec_lookup_phandle(blob, node, "phys");
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if (node <= 0) {
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debug("Not found usb phy device\n");
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return -ENODEV;
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}
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phy_node = fdt_parent_offset(blob, node);
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if (phy_node <= 0) {
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debug("Not found usb phy device\n");
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return -ENODEV;
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}
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rk3288_otg_data.phy_of_node = phy_node;
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grf_phy_offset = fdtdec_get_addr(blob, node, "reg");
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/* find the grf node */
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node = fdt_node_offset_by_compatible(blob, -1,
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"rockchip,rk3288-grf");
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if (node <= 0) {
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debug("Not found grf device\n");
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return -ENODEV;
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}
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rk3288_otg_data.regs_phy = grf_phy_offset +
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fdtdec_get_addr(blob, node, "reg");
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return dwc2_udc_probe(&rk3288_otg_data);
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}
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int board_usb_cleanup(int index, enum usb_init_type init)
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{
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return 0;
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}
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#endif
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static int do_clock(cmd_tbl_t *cmdtp, int flag, int argc,
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char * const argv[])
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{
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static const struct {
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char *name;
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int id;
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} clks[] = {
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{ "osc", CLK_OSC },
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{ "apll", CLK_ARM },
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{ "dpll", CLK_DDR },
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{ "cpll", CLK_CODEC },
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{ "gpll", CLK_GENERAL },
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#ifdef CONFIG_ROCKCHIP_RK3036
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{ "mpll", CLK_NEW },
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#else
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{ "npll", CLK_NEW },
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#endif
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};
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int ret, i;
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struct udevice *dev;
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ret = rockchip_get_clk(&dev);
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if (ret) {
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printf("clk-uclass not found\n");
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return 0;
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}
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for (i = 0; i < ARRAY_SIZE(clks); i++) {
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struct clk clk;
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ulong rate;
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clk.id = clks[i].id;
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ret = clk_request(dev, &clk);
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if (ret < 0)
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continue;
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rate = clk_get_rate(&clk);
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printf("%s: %lu\n", clks[i].name, rate);
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clk_free(&clk);
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}
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return 0;
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}
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U_BOOT_CMD(
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clock, 2, 1, do_clock,
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"display information about clocks",
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""
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);
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