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https://github.com/brain-hackers/u-boot-brain
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38dba0c2ff
Correct initdram to use phys_size_t to represent the size of dram; instead of changing this all over the place, and correcting all the other random errors I've noticed, create a common initdram that is used by all non-corenet 85xx parts. Most of the initdram() functions were identical, with 2 common differences: 1) DDR tlbs for the fixed_sdram case were set up in initdram() on some boards, and were part of the tlb_table on others. I have changed them all over to the initdram() method - we shouldn't be accessing dram before this point so they don't need to be done sooner, and this seems cleaner. 2) Parts that require the DDR11 erratum workaround had different implementations - I have adopted the version from the Freescale errata document. It also looks like some of the versions were buggy, and, depending on timing, could have resulted in the DDR controller being disabled. This seems bad. The xpedite boards had a common/fsl_8xxx_ddr.c; with this change only the 517 board uses this so I have moved the ddr code into that board's directory in xpedite517x.c Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org> Tested-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
105 lines
2.8 KiB
C
105 lines
2.8 KiB
C
/*
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* Copyright 2009 Extreme Engineering Solutions, Inc.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/processor.h>
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#include <asm/fsl_ddr_sdram.h>
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#include <asm/mmu.h>
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#include <asm/io.h>
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#include <fdt_support.h>
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#include <pca953x.h>
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#include "../common/fsl_8xxx_misc.h"
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#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_PCI)
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extern void ft_board_pci_setup(void *blob, bd_t *bd);
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#endif
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/*
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* Print out which flash was booted from and if booting from the 2nd flash,
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* swap flash chip selects to maintain consistent flash numbering/addresses.
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*/
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static void flash_cs_fixup(void)
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{
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int flash_sel;
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/*
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* Print boot dev and swap flash flash chip selects if booted from 2nd
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* flash. Swapping chip selects presents user with a common memory
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* map regardless of which flash was booted from.
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*/
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flash_sel = !((pca953x_get_val(CONFIG_SYS_I2C_PCA953X_ADDR0) &
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CONFIG_SYS_PCA953X_C0_FLASH_PASS_CS));
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printf("FLASH: Executed from FLASH%d\n", flash_sel ? 2 : 1);
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if (flash_sel) {
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set_lbc_br(0, CONFIG_SYS_BR1_PRELIM);
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set_lbc_or(0, CONFIG_SYS_OR1_PRELIM);
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set_lbc_br(1, CONFIG_SYS_BR0_PRELIM);
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set_lbc_or(1, CONFIG_SYS_OR0_PRELIM);
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}
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}
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int board_early_init_r(void)
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{
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/* Initialize PCA9557 devices */
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pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR0, 0xff, 0);
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pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR1, 0xff, 0);
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pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR2, 0xff, 0);
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pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR3, 0xff, 0);
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flash_cs_fixup();
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return 0;
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}
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phys_size_t initdram(int board_type)
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{
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phys_size_t dram_size = fsl_ddr_sdram();
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#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
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/* Initialize and enable DDR ECC */
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ddr_enable_ecc(dram_size);
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#endif
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return dram_size;
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}
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#if defined(CONFIG_OF_BOARD_SETUP)
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void ft_board_setup(void *blob, bd_t *bd)
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{
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#ifdef CONFIG_PCI
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ft_board_pci_setup(blob, bd);
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#endif
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ft_cpu_setup(blob, bd);
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}
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#endif
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#ifdef CONFIG_MP
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extern void cpu_mp_lmb_reserve(struct lmb *lmb);
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void board_lmb_reserve(struct lmb *lmb)
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{
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cpu_mp_lmb_reserve(lmb);
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}
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#endif
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