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![Tom Rini](/assets/img/avatar_default.png)
Introduce a __weak misc_init_r function that just runs dieid_num_r(). Remove misc_init_r from cm_t35, mcx, omap3_logic and mt_ventoux as this was all they did for misc_init_r. Cc: Igor Grinberg <grinberg@compulab.co.il> Cc: Ilya Yanok <yanok@emcraft.com> Cc: Peter Barada <peter.barada@logicpd.com> Cc: Stefano Babic <sbabic@denx.de> Signed-off-by: Tom Rini <trini@ti.com> Acked-by: Igor Grinberg <grinberg@compulab.co.il>
227 lines
4.7 KiB
C
227 lines
4.7 KiB
C
/*
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* Copyright (C) 2011
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* Stefano Babic, DENX Software Engineering, sbabic@denx.de.
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*
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* Copyright (C) 2009 TechNexion Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc.
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*/
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#include <common.h>
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#include <netdev.h>
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#include <fpga.h>
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#include <asm/io.h>
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#include <asm/arch/mem.h>
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#include <asm/arch/mux.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/omap_gpio.h>
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#include <asm/arch/mmc_host_def.h>
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#include <i2c.h>
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#include <spartan3.h>
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#include <asm/gpio.h>
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#ifdef CONFIG_USB_EHCI
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#include <usb.h>
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#include <asm/ehci-omap.h>
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#endif
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#include "mt_ventoux.h"
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DECLARE_GLOBAL_DATA_PTR;
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#ifndef CONFIG_FPGA
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#error "The Teejet mt_ventoux must have CONFIG_FPGA enabled"
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#endif
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#define FPGA_RESET 62
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#define FPGA_PROG 116
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#define FPGA_CCLK 117
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#define FPGA_DIN 118
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#define FPGA_INIT 119
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#define FPGA_DONE 154
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/* Timing definitions for FPGA */
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static const u32 gpmc_fpga[] = {
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FPGA_GPMC_CONFIG1,
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FPGA_GPMC_CONFIG2,
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FPGA_GPMC_CONFIG3,
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FPGA_GPMC_CONFIG4,
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FPGA_GPMC_CONFIG5,
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FPGA_GPMC_CONFIG6,
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};
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#ifdef CONFIG_USB_EHCI
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static struct omap_usbhs_board_data usbhs_bdata = {
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.port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
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.port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
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.port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
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};
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int ehci_hcd_init(void)
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{
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return omap_ehci_hcd_init(&usbhs_bdata);
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}
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int ehci_hcd_stop(void)
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{
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return omap_ehci_hcd_stop();
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}
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#endif
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static inline void fpga_reset(int nassert)
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{
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gpio_set_value(FPGA_RESET, !nassert);
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}
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int fpga_pgm_fn(int nassert, int nflush, int cookie)
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{
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debug("%s:%d: FPGA PROGRAM ", __func__, __LINE__);
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gpio_set_value(FPGA_PROG, !nassert);
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return nassert;
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}
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int fpga_init_fn(int cookie)
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{
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return !gpio_get_value(FPGA_INIT);
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}
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int fpga_done_fn(int cookie)
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{
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return gpio_get_value(FPGA_DONE);
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}
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int fpga_pre_config_fn(int cookie)
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{
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debug("%s:%d: FPGA pre-configuration\n", __func__, __LINE__);
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/* Setting GPIOs for programming Mode */
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gpio_request(FPGA_RESET, "FPGA_RESET");
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gpio_direction_output(FPGA_RESET, 1);
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gpio_request(FPGA_PROG, "FPGA_PROG");
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gpio_direction_output(FPGA_PROG, 1);
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gpio_request(FPGA_CCLK, "FPGA_CCLK");
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gpio_direction_output(FPGA_CCLK, 1);
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gpio_request(FPGA_DIN, "FPGA_DIN");
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gpio_direction_output(FPGA_DIN, 0);
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gpio_request(FPGA_INIT, "FPGA_INIT");
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gpio_direction_input(FPGA_INIT);
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gpio_request(FPGA_DONE, "FPGA_DONE");
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gpio_direction_input(FPGA_DONE);
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/* Be sure that signal are deasserted */
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gpio_set_value(FPGA_RESET, 1);
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gpio_set_value(FPGA_PROG, 1);
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return 0;
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}
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int fpga_post_config_fn(int cookie)
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{
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debug("%s:%d: FPGA post-configuration\n", __func__, __LINE__);
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fpga_reset(TRUE);
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udelay(100);
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fpga_reset(FALSE);
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return 0;
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}
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/* Write program to the FPGA */
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int fpga_wr_fn(int nassert_write, int flush, int cookie)
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{
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gpio_set_value(FPGA_DIN, nassert_write);
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return nassert_write;
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}
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int fpga_clk_fn(int assert_clk, int flush, int cookie)
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{
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gpio_set_value(FPGA_CCLK, assert_clk);
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return assert_clk;
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}
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Xilinx_Spartan3_Slave_Serial_fns mt_ventoux_fpga_fns = {
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fpga_pre_config_fn,
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fpga_pgm_fn,
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fpga_clk_fn,
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fpga_init_fn,
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fpga_done_fn,
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fpga_wr_fn,
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fpga_post_config_fn,
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};
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Xilinx_desc fpga = XILINX_XC6SLX4_DESC(slave_serial,
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(void *)&mt_ventoux_fpga_fns, 0);
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/* Initialize the FPGA */
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static void mt_ventoux_init_fpga(void)
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{
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fpga_pre_config_fn(0);
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/* Setting CS1 for FPGA access */
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enable_gpmc_cs_config(gpmc_fpga, &gpmc_cfg->cs[1],
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FPGA_BASE_ADDR, GPMC_SIZE_128M);
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fpga_init();
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fpga_add(fpga_xilinx, &fpga);
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}
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/*
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* Routine: board_init
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* Description: Early hardware init.
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*/
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int board_init(void)
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{
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gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
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/* boot param addr */
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gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
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mt_ventoux_init_fpga();
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return 0;
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}
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/*
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* Routine: set_muxconf_regs
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* Description: Setting up the configuration Mux registers specific to the
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* hardware. Many pins need to be moved from protect to primary
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* mode.
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*/
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void set_muxconf_regs(void)
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{
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MUX_MT_VENTOUX();
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}
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/*
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* Initializes on-chip ethernet controllers.
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* to override, implement board_eth_init()
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*/
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int board_eth_init(bd_t *bis)
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{
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davinci_emac_initialize();
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return 0;
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}
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#if defined(CONFIG_OMAP_HSMMC) && \
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!defined(CONFIG_SPL_BUILD)
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int board_mmc_init(bd_t *bis)
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{
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return omap_mmc_init(0, 0, 0);
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}
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#endif
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