mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-31 15:23:45 +09:00
38cee12dcf
"reset altbank" will reset another bank WITHOUT watch dog timer enabled
"reset altbank wd" will reset another bank WITH watch dog enabled
"diswd" will disable watch dog after u-boot boots up successfully
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
681 lines
16 KiB
C
681 lines
16 KiB
C
/*
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* Copyright 2004 Freescale Semiconductor
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* Jeff Brown (jeffrey@freescale.com)
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* Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <watchdog.h>
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#include <command.h>
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#include <asm/cache.h>
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#include <mpc86xx.h>
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#if defined(CONFIG_OF_FLAT_TREE)
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#include <ft_build.h>
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#endif
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extern unsigned long get_board_sys_clk(ulong dummy);
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static __inline__ unsigned long get_dbat3u (void)
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{
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unsigned long dbat3u;
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asm volatile("mfspr %0, 542" : "=r" (dbat3u) :);
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return dbat3u;
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}
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static __inline__ unsigned long get_dbat3l (void)
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{
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unsigned long dbat3l;
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asm volatile("mfspr %0, 543" : "=r" (dbat3l) :);
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return dbat3l;
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}
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static __inline__ unsigned long get_msr (void)
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{
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unsigned long msr;
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asm volatile("mfmsr %0" : "=r" (msr) :);
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return msr;
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}
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int checkcpu (void)
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{
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sys_info_t sysinfo;
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uint pvr, svr;
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uint ver;
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uint major, minor;
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uint lcrr; /* local bus clock ratio register */
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uint clkdiv; /* clock divider portion of lcrr */
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puts("Freescale PowerPC\n");
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pvr = get_pvr();
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ver = PVR_VER(pvr);
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major = PVR_MAJ(pvr);
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minor = PVR_MIN(pvr);
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puts("CPU:\n");
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printf(" Core: ");
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switch (ver) {
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case PVR_VER(PVR_86xx):
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puts("E600");
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break;
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default:
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puts("Unknown");
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break;
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}
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printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr);
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svr = get_svr();
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ver = SVR_VER(svr);
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major = SVR_MAJ(svr);
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minor = SVR_MIN(svr);
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puts(" System: ");
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switch (ver) {
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case SVR_8641:
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puts("8641");
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break;
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case SVR_8641D:
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puts("8641D");
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break;
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default:
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puts("Unknown");
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break;
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}
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printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr);
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get_sys_info(&sysinfo);
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puts(" Clocks: ");
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printf("CPU:%4lu MHz, ", sysinfo.freqProcessor / 1000000);
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printf("MPX:%4lu MHz, ", sysinfo.freqSystemBus / 1000000);
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printf("DDR:%4lu MHz, ", sysinfo.freqSystemBus / 2000000);
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#if defined(CFG_LBC_LCRR)
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lcrr = CFG_LBC_LCRR;
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#else
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{
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volatile immap_t *immap = (immap_t *)CFG_IMMR;
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volatile ccsr_lbc_t *lbc= &immap->im_lbc;
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lcrr = lbc->lcrr;
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}
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#endif
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clkdiv = lcrr & 0x0f;
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if (clkdiv == 2 || clkdiv == 4 || clkdiv == 8) {
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printf("LBC:%4lu MHz\n",
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sysinfo.freqSystemBus / 1000000 / clkdiv);
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} else {
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printf(" LBC: unknown (lcrr: 0x%08x)\n", lcrr);
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}
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printf(" L2: ");
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if (get_l2cr() & 0x80000000)
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printf("Enabled\n");
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else
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printf("Disabled\n");
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return 0;
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}
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/* -------------------------------------------------------------------- */
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static inline void
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soft_restart(unsigned long addr)
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{
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#ifndef CONFIG_MPC8641HPCN
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/* SRR0 has system reset vector, SRR1 has default MSR value */
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/* rfi restores MSR from SRR1 and sets the PC to the SRR0 value */
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__asm__ __volatile__ ("mtspr 26, %0" :: "r" (addr));
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__asm__ __volatile__ ("li 4, (1 << 6)" ::: "r4");
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__asm__ __volatile__ ("mtspr 27, 4");
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__asm__ __volatile__ ("rfi");
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#else /* CONFIG_MPC8641HPCN */
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out8(PIXIS_BASE+PIXIS_RST,0);
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#endif /* !CONFIG_MPC8641HPCN */
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while(1); /* not reached */
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}
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#ifdef CONFIG_MPC8641HPCN
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int set_px_sysclk(ulong sysclk)
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{
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u8 sysclk_s, sysclk_r, sysclk_v, vclkh, vclkl, sysclk_aux;
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/* Per table 27, page 58 of MPC8641HPCN spec*/
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switch(sysclk)
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{
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case 33:
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sysclk_s = 0x04;
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sysclk_r = 0x04;
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sysclk_v = 0x07;
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sysclk_aux = 0x00;
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break;
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case 40:
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sysclk_s = 0x01;
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sysclk_r = 0x1F;
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sysclk_v = 0x20;
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sysclk_aux = 0x01;
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break;
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case 50:
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sysclk_s = 0x01;
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sysclk_r = 0x1F;
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sysclk_v = 0x2A;
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sysclk_aux = 0x02;
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break;
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case 66:
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sysclk_s = 0x01;
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sysclk_r = 0x04;
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sysclk_v = 0x04;
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sysclk_aux = 0x03;
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break;
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case 83:
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sysclk_s = 0x01;
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sysclk_r = 0x1F;
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sysclk_v = 0x4B;
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sysclk_aux = 0x04;
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break;
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case 100:
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sysclk_s = 0x01;
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sysclk_r = 0x1F;
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sysclk_v = 0x5C;
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sysclk_aux = 0x05;
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break;
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case 134:
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sysclk_s = 0x06;
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sysclk_r = 0x1F;
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sysclk_v = 0x3B;
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sysclk_aux = 0x06;
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break;
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case 166:
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sysclk_s = 0x06;
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sysclk_r = 0x1F;
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sysclk_v = 0x4B;
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sysclk_aux = 0x07;
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break;
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default:
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printf("Unsupported SYSCLK frequency.\n");
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return 0;
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}
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vclkh = (sysclk_s << 5) | sysclk_r ;
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vclkl = sysclk_v;
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out8(PIXIS_BASE+PIXIS_VCLKH,vclkh);
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out8(PIXIS_BASE+PIXIS_VCLKL,vclkl);
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out8(PIXIS_BASE+PIXIS_AUX,sysclk_aux);
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return 1;
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}
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int set_px_mpxpll(ulong mpxpll)
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{
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u8 tmp;
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u8 val;
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switch(mpxpll)
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{
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case 2:
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case 4:
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case 6:
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case 8:
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case 10:
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case 12:
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case 14:
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case 16:
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val = (u8)mpxpll;
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break;
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default:
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printf("Unsupported MPXPLL ratio.\n");
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return 0;
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}
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tmp = in8(PIXIS_BASE+PIXIS_VSPEED1);
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tmp = (tmp & 0xF0) | (val & 0x0F);
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out8(PIXIS_BASE+PIXIS_VSPEED1,tmp);
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return 1;
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}
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int set_px_corepll(ulong corepll)
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{
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u8 tmp;
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u8 val;
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switch ((int)corepll) {
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case 20:
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val = 0x08;
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break;
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case 25:
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val = 0x0C;
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break;
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case 30:
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val = 0x10;
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break;
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case 35:
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val = 0x1C;
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break;
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case 40:
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val = 0x14;
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break;
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case 45:
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val = 0x0E;
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break;
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default:
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printf("Unsupported COREPLL ratio.\n");
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return 0;
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}
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tmp = in8(PIXIS_BASE+PIXIS_VSPEED0);
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tmp = (tmp & 0xE0) | (val & 0x1F);
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out8(PIXIS_BASE+PIXIS_VSPEED0,tmp);
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return 1;
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}
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void read_from_px_regs(int set)
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{
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u8 tmp, mask = 0x1C;
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tmp = in8(PIXIS_BASE+PIXIS_VCFGEN0);
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if (set)
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tmp = tmp | mask;
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else
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tmp = tmp & ~mask;
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out8(PIXIS_BASE+PIXIS_VCFGEN0,tmp);
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}
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void read_from_px_regs_altbank(int set)
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{
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u8 tmp, mask = 0x04;
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tmp = in8(PIXIS_BASE+PIXIS_VCFGEN1);
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if (set)
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tmp = tmp | mask;
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else
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tmp = tmp & ~mask;
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out8(PIXIS_BASE+PIXIS_VCFGEN1,tmp);
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}
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void set_altbank(void)
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{
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u8 tmp;
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tmp = in8(PIXIS_BASE+PIXIS_VBOOT);
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tmp ^= 0x40;
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out8(PIXIS_BASE+PIXIS_VBOOT,tmp);
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}
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void set_px_go(void)
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{
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u8 tmp;
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tmp = in8(PIXIS_BASE+PIXIS_VCTL);
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tmp = tmp & 0x1E;
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out8(PIXIS_BASE+PIXIS_VCTL,tmp);
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tmp = in8(PIXIS_BASE+PIXIS_VCTL);
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tmp = tmp | 0x01;
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out8(PIXIS_BASE+PIXIS_VCTL,tmp);
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}
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void set_px_go_with_watchdog(void)
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{
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u8 tmp;
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tmp = in8(PIXIS_BASE+PIXIS_VCTL);
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tmp = tmp & 0x1E;
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out8(PIXIS_BASE+PIXIS_VCTL,tmp);
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tmp = in8(PIXIS_BASE+PIXIS_VCTL);
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tmp = tmp | 0x09;
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out8(PIXIS_BASE+PIXIS_VCTL,tmp);
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}
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int disable_watchdog(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
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{
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u8 tmp;
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tmp = in8(PIXIS_BASE+PIXIS_VCTL);
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tmp = tmp & 0x1E;
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out8(PIXIS_BASE+PIXIS_VCTL,tmp);
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tmp = in8(PIXIS_BASE + PIXIS_VCTL);
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tmp &= ~ 0x08; /* setting VCTL[WDEN] to 0 to disable watch dog */
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out8(PIXIS_BASE + PIXIS_VCTL, tmp);
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return 0;
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}
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U_BOOT_CMD(
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diswd, 1, 0, disable_watchdog,
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"diswd - Disable watchdog timer \n",
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NULL
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);
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/* This function takes the non-integral cpu:mpx pll ratio
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* and converts it to an integer that can be used to assign
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* FPGA register values.
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* input: strptr i.e. argv[2]
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*/
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ulong strfractoint(uchar *strptr)
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{
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int i,j,retval,intarr_len=0, decarr_len=0, mulconst, no_dec=0;
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ulong intval =0, decval=0;
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uchar intarr[3], decarr[3];
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/* Assign the integer part to intarr[]
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* If there is no decimal point i.e.
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* if the ratio is an integral value
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* simply create the intarr.
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*/
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i=0;
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while(strptr[i] != 46)
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{
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if(strptr[i] == 0)
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{
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no_dec = 1;
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break; /* Break from loop once the end of string is reached */
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}
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intarr[i] = strptr[i];
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i++;
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}
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intarr_len = i; /* Assign length of integer part to intarr_len*/
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intarr[i] = '\0'; /* */
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if(no_dec)
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{
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mulconst=10; /* Currently needed only for single digit corepll ratios */
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decval = 0;
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}
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else
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{
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j=0;
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i++; /* Skipping the decimal point */
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while ((strptr[i] > 47) && (strptr[i] < 58))
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{
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decarr[j] = strptr[i];
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i++;
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j++;
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}
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decarr_len = j;
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decarr[j] = '\0';
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mulconst=1;
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for(i=0; i<decarr_len;i++)
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mulconst = mulconst*10;
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decval = simple_strtoul(decarr,NULL,10);
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}
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intval = simple_strtoul(intarr,NULL,10);
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intval = intval*mulconst;
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retval = intval+decval;
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return retval;
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}
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#endif /* CONFIG_MPC8641HPCN */
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/* no generic way to do board reset. simply call soft_reset. */
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void
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do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
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{
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char cmd;
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ulong addr, val;
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ulong corepll;
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#ifdef CFG_RESET_ADDRESS
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addr = CFG_RESET_ADDRESS;
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#else
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/*
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* note: when CFG_MONITOR_BASE points to a RAM address,
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* CFG_MONITOR_BASE - sizeof (ulong) is usually a valid
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* address. Better pick an address known to be invalid on your
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* system and assign it to CFG_RESET_ADDRESS.
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*/
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addr = CFG_MONITOR_BASE - sizeof (ulong);
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#endif
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#ifndef CONFIG_MPC8641HPCN
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/* flush and disable I/D cache */
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__asm__ __volatile__ ("mfspr 3, 1008" ::: "r3");
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__asm__ __volatile__ ("ori 5, 5, 0xcc00" ::: "r5");
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__asm__ __volatile__ ("ori 4, 3, 0xc00" ::: "r4");
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__asm__ __volatile__ ("andc 5, 3, 5" ::: "r5");
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__asm__ __volatile__ ("sync");
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__asm__ __volatile__ ("mtspr 1008, 4");
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__asm__ __volatile__ ("isync");
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__asm__ __volatile__ ("sync");
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__asm__ __volatile__ ("mtspr 1008, 5");
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__asm__ __volatile__ ("isync");
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__asm__ __volatile__ ("sync");
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soft_restart(addr);
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#else /* CONFIG_MPC8641HPCN */
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if (argc > 1) {
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cmd = argv[1][1];
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switch(cmd) {
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case 'f': /* reset with frequency changed */
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if (argc < 5)
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goto my_usage;
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read_from_px_regs(0);
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val = set_px_sysclk(simple_strtoul(argv[2],NULL,10));
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corepll = strfractoint(argv[3]);
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val = val + set_px_corepll(corepll);
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val = val + set_px_mpxpll(simple_strtoul(argv[4],
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NULL, 10));
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if (val == 3) {
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printf("Setting registers VCFGEN0 and VCTL\n");
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read_from_px_regs(1);
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printf("Resetting board with values from VSPEED0, VSPEED1, VCLKH, and VCLKL ....\n");
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set_px_go();
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} else
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goto my_usage;
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while (1); /* Not reached */
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case 'l':
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if (argv[2][1] == 'f') {
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read_from_px_regs(0);
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read_from_px_regs_altbank(0);
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/* reset with frequency changed */
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val = set_px_sysclk(simple_strtoul(argv[3],NULL,10));
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corepll = strfractoint(argv[4]);
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val = val + set_px_corepll(corepll);
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val = val + set_px_mpxpll(simple_strtoul(argv[5],NULL,10));
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if (val == 3) {
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printf("Setting registers VCFGEN0, VCFGEN1, VBOOT, and VCTL\n");
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set_altbank();
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read_from_px_regs(1);
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read_from_px_regs_altbank(1);
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printf("Enabling watchdog timer on the FPGA and resetting board with values from VSPEED0, VSPEED1, VCLKH, and VCLKL to boot from the other bank ....\n");
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set_px_go_with_watchdog();
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} else
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goto my_usage;
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while(1); /* Not reached */
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} else if(argv[2][1] == 'd'){
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/* Reset from next bank without changing frequencies but with watchdog timer enabled */
|
|
read_from_px_regs(0);
|
|
read_from_px_regs_altbank(0);
|
|
printf("Setting registers VCFGEN1, VBOOT, and VCTL\n");
|
|
set_altbank();
|
|
read_from_px_regs_altbank(1);
|
|
printf("Enabling watchdog timer on the FPGA and resetting board to boot from the other bank....\n");
|
|
set_px_go_with_watchdog();
|
|
while(1); /* Not reached */
|
|
} else {
|
|
/* Reset from next bank without changing frequency and without watchdog timer enabled */
|
|
read_from_px_regs(0);
|
|
read_from_px_regs_altbank(0);
|
|
if(argc > 2)
|
|
goto my_usage;
|
|
printf("Setting registers VCFGNE1, VBOOT, and VCTL\n");
|
|
set_altbank();
|
|
read_from_px_regs_altbank(1);
|
|
printf("Resetting board to boot from the other bank....\n");
|
|
set_px_go();
|
|
}
|
|
|
|
default:
|
|
goto my_usage;
|
|
}
|
|
|
|
my_usage:
|
|
printf("\nUsage: reset cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>\n");
|
|
printf(" reset altbank [cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>]\n");
|
|
printf("For example: reset cf 40 2.5 10\n");
|
|
printf("See MPC8641HPCN Design Workbook for valid values of command line parameters.\n");
|
|
return;
|
|
} else
|
|
out8(PIXIS_BASE+PIXIS_RST,0);
|
|
|
|
#endif /* !CONFIG_MPC8641HPCN */
|
|
|
|
while(1); /* not reached */
|
|
}
|
|
|
|
|
|
/*
|
|
* Get timebase clock frequency
|
|
*/
|
|
unsigned long get_tbclk(void)
|
|
{
|
|
sys_info_t sys_info;
|
|
|
|
get_sys_info(&sys_info);
|
|
return (sys_info.freqSystemBus + 3L) / 4L;
|
|
}
|
|
|
|
|
|
#if defined(CONFIG_WATCHDOG)
|
|
void
|
|
watchdog_reset(void)
|
|
{
|
|
}
|
|
#endif /* CONFIG_WATCHDOG */
|
|
|
|
|
|
#if defined(CONFIG_DDR_ECC)
|
|
void dma_init(void)
|
|
{
|
|
volatile immap_t *immap = (immap_t *)CFG_IMMR;
|
|
volatile ccsr_dma_t *dma = &immap->im_dma;
|
|
|
|
dma->satr0 = 0x00040000;
|
|
dma->datr0 = 0x00040000;
|
|
asm("sync; isync");
|
|
return;
|
|
}
|
|
|
|
uint dma_check(void)
|
|
{
|
|
volatile immap_t *immap = (immap_t *)CFG_IMMR;
|
|
volatile ccsr_dma_t *dma = &immap->im_dma;
|
|
volatile uint status = dma->sr0;
|
|
|
|
/* While the channel is busy, spin */
|
|
while((status & 4) == 4) {
|
|
status = dma->sr0;
|
|
}
|
|
|
|
if (status != 0) {
|
|
printf ("DMA Error: status = %x\n", status);
|
|
}
|
|
return status;
|
|
}
|
|
|
|
int dma_xfer(void *dest, uint count, void *src)
|
|
{
|
|
volatile immap_t *immap = (immap_t *)CFG_IMMR;
|
|
volatile ccsr_dma_t *dma = &immap->im_dma;
|
|
|
|
dma->dar0 = (uint) dest;
|
|
dma->sar0 = (uint) src;
|
|
dma->bcr0 = count;
|
|
dma->mr0 = 0xf000004;
|
|
asm("sync;isync");
|
|
dma->mr0 = 0xf000005;
|
|
asm("sync;isync");
|
|
return dma_check();
|
|
}
|
|
|
|
#endif /* CONFIG_DDR_ECC */
|
|
|
|
|
|
#ifdef CONFIG_OF_FLAT_TREE
|
|
void ft_cpu_setup(void *blob, bd_t *bd)
|
|
{
|
|
u32 *p;
|
|
ulong clock;
|
|
int len;
|
|
|
|
clock = bd->bi_busfreq;
|
|
p = ft_get_prop(blob, "/cpus/" OF_CPU "/bus-frequency", &len);
|
|
if (p != NULL)
|
|
*p = cpu_to_be32(clock);
|
|
|
|
p = ft_get_prop(blob, "/" OF_SOC "/serial@4500/clock-frequency", &len);
|
|
if (p != NULL)
|
|
*p = cpu_to_be32(clock);
|
|
|
|
p = ft_get_prop(blob, "/" OF_SOC "/serial@4600/clock-frequency", &len);
|
|
if (p != NULL)
|
|
*p = cpu_to_be32(clock);
|
|
|
|
#if defined(CONFIG_MPC86XX_TSEC1)
|
|
p = ft_get_prop(blob, "/" OF_SOC "/ethernet@24000/address", &len);
|
|
memcpy(p, bd->bi_enetaddr, 6);
|
|
#endif
|
|
|
|
#if defined(CONFIG_MPC86XX_TSEC2)
|
|
p = ft_get_prop(blob, "/" OF_SOC "/ethernet@25000/address", &len);
|
|
memcpy(p, bd->bi_enet1addr, 6);
|
|
#endif
|
|
|
|
#if defined(CONFIG_MPC86XX_TSEC3)
|
|
p = ft_get_prop(blob, "/" OF_SOC "/ethernet@26000/address", &len);
|
|
memcpy(p, bd->bi_enet2addr, 6);
|
|
#endif
|
|
|
|
#if defined(CONFIG_MPC86XX_TSEC4)
|
|
p = ft_get_prop(blob, "/" OF_SOC "/ethernet@27000/address", &len);
|
|
memcpy(p, bd->bi_enet3addr, 6);
|
|
#endif
|
|
|
|
}
|
|
#endif
|